Skew Compensation Technique Research Articles

An Efficient Method for Skew Estimation and Compensation in Coherent Receivers

The performance of coherent optical systems can be seriously degraded when in-phase and quadrature (IQ) components experience misalignments crossing certain critical limits. The critical limits of IQ phase, gain, and skew misalignments are lower at higher modulation formats and in narrowband systems. In this letter, frequency-domain skew-estimation algorithm and time-domain skew-compensation technique are proposed. When compared with other published methods, the new architecture improves timing performance and relaxes requirements for a multiple-input multiple-output time-domain equalizer at low implementation price. We discuss IQ imperfections on both transmitter and receiver sides and provide an efficient compensation procedure.

Common Phase Estimation in Coherent OFDM System Using Image Processing Technique

In a coherent orthogonal frequency division multiplexing system, the possible rotation of the rectangular signal constellation, due to common phase error, is shown to be effectively compensated by applying an skew compensation technique adopted in image processing area. We further propose an improved technique to further reduce the complexity of the algorithm and investigate the effect of the number of required test phases, via numerical simulations. The proposed improved algorithm is also compared with the conventional blind phase searching algorithm. It is shown that by employing only two bits of overhead, it can achieve a comparable performance to that of the traditional pilot aided method.

Inter-signal timing skew compensation of parallel links with current-mode incremental signalling

This study proposes a new inter-signal timing skew compensation technique for parallel links with current-mode incremental signalling. The maximum deskew range is one bit time in both directions. Both the transmitters and receivers of the links are current-mode configured to take the advantages of current-mode signalling. Each receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values, enabling a convenient recovery of both the logic state and timing information of the received data. The feedback at the front-end of the receiver minimises the dependence of the input impedance of the receiver on the direction of the channel current so that data-dependent impedance mismatch is minimised. Inter-signal timing skews are compensated by inserting a delay line in each channel whose time delay is determined by the phase difference between the master sampling clock and data. A voltage replication circuit is proposed to copy the obtained optimal control voltage of the delay line of each channel so that the optimal deskew control voltage of the delay line is sustained. To assess the effectiveness of the proposed inter-signal timing skew compensation technique, a 2-bit 1 Gbytes/s parallel link has been implemented in UMC-0.13 mum 1.2 V CMOS technology and analysed using SpectreRF with BSIM3V3 device models. Simulation results demonstrate that the proposed inter-signal timing skew compensation method can compensate inter-signal timing skew up to one bit time in both directions.

Parallel links with current-mode incremental signaling and per-pin skew compensation

This paper proposes a new inter-signal timing skew compensation technique for parallel links with current-mode incremental signaling. Both the transmitter and receiver of the links are current-mode configured to utilize the intrinsic advantages of current-mode signaling. The receiver maps the direction of its channel currents representing the logic state of the incoming data to two voltages whose values are largely different, enabling a convenient recovery of both the logic state and timing information of the received current-mode data in the voltage-mode domain, and suppression of the common-mode disturbances coupled to the channels. Inter-signal timing skews are compensated by inserting a delay line in each channel whose time delay is determined by the phase difference between the transmitted master clock and the output of the recovering comparator. To assess the effectiveness of the proposed inter-signal timing skew compensation technique, a 2-bit 1Gbytes/s parallel link has been designed in IBM-0.13μm1.2V CMOS technology and analyzed using SpectreRF with BSIM3V3 device models. Simulation results of the parallel link with the proposed deskewing scheme demonstrate that inter-signal timing skews can be effectively compensated using the proposed deskewing scheme.

A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM

This paper describes a 5-GByte/s data-transfer scheme suitable for synchronous DRAM memory. To achieve a higher data-transfer frequency, the properties were improved based on the frequency analysis of the memory system. Then, a bit-to-bit skew compensation technique that eliminates incongruent skew between the signals is described with a new, multioutput controlled delay circuit to accomplish bit-to-bit skew compensation by controlling transmission timing of every data bit. Simulated maximum data-transfer rate of the proposed memory system resulted in 5.1/5.8 GByte/s (321/365 MHz, /spl times/64 bit, double data rate) for data write/read operation, respectively.