Single-writer Multi-reader Research Articles

On atomic registers and randomized consensus in M&M systems

Motivated by recent distributed systems technology, Aguilera et al. introduced a hybrid model of distributed computing, called the message-and-memory model or m&m model for short. In this model, processes can communicate by message passing and also by accessing some shared memory (e.g., through some RDMA connections). We first consider the basic problem of implementing an atomic single-writer multi-reader (SWMR) register shared by all the processes in m&m systems. Specifically, we give an algorithm that implements such a register in m&m systems and show that it is optimal in the number of process crashes that it tolerates. This generalizes the well-known ABD implementation of an atomic SWMR register in a pure message-passing system. We then combine our register implementation for m&m systems with a randomized consensus algorithm of Aspnes and Herlihy, and obtain a randomized consensus algorithm for m&m systems that is also optimal in the number of process crashes that it can tolerate. Finally, we determine the minimum number of RDMA connections that is sufficient to implement a SWMR register, or solve randomized consensus, in an m&m system with t process crashes, for any given t.

Multi-writer Multi-reader Boolean Keyword Searchable Encryption

In traditional public key searchable encryption (PKSE), a data owner (writer) utilizes data user’s (reader) public key to build ciphertexts. Thus, to share D data items (W keywords per item) with R readers, a writer suffers from $$O(R \cdot D \cdot W)$$ computational overhead. Researchers then offer numerous schemes supporting multiple readers with optimal overhead, i.e., $$O(D \cdot W)$$ . However, these schemes support either a single-keyword search or multi-keyword search in single-writer multi-reader (SWMR) setting where a writer could share data with the known set of readers. On the other hand, the existing multi-writer multi-reader (MWMR) PKSE offers Boolean search but suffers from $$O(R \cdot D \cdot W)$$ computational overhead for each writer. We observe applications desiring PKSE where writers could share data with the unknown set of readers and readers could perform search across data for Boolean query. Since the existing literature lacks such schemes, we propose a multi-writer multi-reader Boolean keyword searchable encryption (MWMR-BKSE) where the separate sets of registered readers and writers are prepared. Once registered, the writer could compute ciphertexts without knowing the potential readers and the readers could search across data at any time. The computational overhead on each writer is optimal $$O(D \cdot W)$$ . Additionally, a deregistered client would not be able to further write or read data. With MWMR-BKSE, we offer a Boolean keyword search utilizing key policy attribute-based encryption. The security of ciphertext against chosen keyword attack is proved using full security model. With the detailed theoretical analysis and extensive simulations on real-world datasets, we demonstrate the effectiveness of MWMR-BKSE.

Implementing Snapshot Objects on Top of Crash-Prone Asynchronous Message-Passing Systems

In asynchronous crash-prone read/write shared-memory systems there is the notion of a snapshot object, which simulates the behavior of an array of single-writer/multi-reader (SWMR) shared registers that can be read atomically. Processes in the system can access the object invoking (any number of times) two operations, denoted $\mathsf {write}()$ and $\mathsf {snapshot}()$ . A process invokes $\mathsf {write}()$ to update the value of its register in the array. When it invokes $\mathsf {snapshot}()$ , the process obtains the values of all registers, as if it read them simultaneously. It is known that a snapshot object can be implemented on top of SWMR registers, tolerating any number of process failures. Snapshot objects provide a level of abstraction higher than individual SWMR registers, and they simplify the design of applications. Building a snapshot object on an asynchronous crash-prone message-passing system has similar benefits. The object can be implemented by using the known simulations of a SWMR shared memory on top of an asynchronous message-passing system (if less than half the processes can crash), and then build a snapshot object on top of the simulated SWMR memory. This paper presents an algorithm that implements a snapshot object directly on top of the message-passing system, without building an intermediate layer of a SWMR shared memory. To the authors knowledge, the proposed algorithm is the first providing such a direct construction. The algorithm is more efficient than the indirect solution, yet relatively simple.

Linear space bootstrap communication schemes

Consider a system of n processes with ids that are drawn from a large space. How can these n processes communicate to solve a problem? It is shown that linear number of Multi-Writer Multi-Reader (MWMR) registers are sufficient to solve any read-write wait-free solvable problem and needed to solve some read-write wait-free solvable problem. This contrasts with the existing possible solution borrowed from adaptive algorithms that require Θ(n3/2) MWMR registers.To obtain the sufficiency result, the paper shows how the processes can non-blocking emulate a system of n Single-Writer Multi-Reader (SWMR) registers on top of n Multi-Writer Multi-Reader (MWMR) registers. For the necessity result, it shows it is impossible to do such an emulation with n−1 MWMR registers.The paper also presents a wait-free emulation, using 2n−1 rather than just n registers. The emulation can be used to solve an infinite sequence of tasks that are sequentially dependent (processes need the previous task's outputs in order to proceed to the next task). A non-blocking emulation cannot be used in this case, because it might starve a process forever.

Efficient and Robust Sharing of Memory in Message-Passing Systems

A simulation of a wait-free, atomic, single-writer multireader register in an asynchronous message passing system is presented. The simulation can withstand the failure of up to half of the processors and requires O(n) messages (for each read or write operation), assuming there are n+1 processors in the system. It improves on the previous simulation, which requires O(n2) messages (for each read or write operation). The message complexity of the new simulation is within a constant factor of the optimum. The new simulation improves the complexity of algorithms for the following problems in the message-passing model in the presence of processor failures: multiwriter multireader registers, concurrent time-stamp systems, ℓ-exclusion, atomic snapshots, randomized consensus, implementation of data structures, as well as improved fault-tolerant algorithms for any solvable decision task.