Test Set For Single Stuck-at Faults Research Articles

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage.

Test set compaction algorithms for combinational circuits

This paper presents a new algorithm, essential fault reduction, for generating compact test sets for combinational circuits under the single stuck-at fault model, and a new heuristic for estimating the minimum single stuck-at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced automatic test pattern generation system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan versions of the ISCAS89 benchmark circuits.

Detection of multiple faults using SSFTS in CMOS logic circuits

With the increasing density of CMOS VLSI circuits, it is necessary to test for the combinations of different multiple faults. This paper studies the possibility of using single stuck-at fault test set (SSFTS) to detect multiple faults and their combinations. The paper shows that a single stuck-at-fault test set can detect single and multiple self-feedback bridging faults, combinations of feedback bridging, input bridging and stuck-on faults when current monitoring is done. We also prove that a single stuck-at fault test set can detect the combination of single stuck-open fault and some other faults like bridging and stuck-on faults when both logic and current monitoring are done.