Single-stage LNA Research Articles

Impact of RF stress on different topologies of 100 nm X-band robust GaN LNA

In this article, we study the robustness of 3 versions of a single stage LNA configured according to different modes of detectivity or robustness against electromagnetic jamming signals. Four successive sequences of RF step stress at 10 GHz are applied to each of the 3 LNAs under study. These robust MMIC LNAs have been designed using the D01GH GaN process from OMMIC technology, to switch from a nominal low noise mode to a high linearity mode. This DC-bias switch allows increasing the power input 1 dB compression point by 8 dB. This study focuses on the robustness of these LNAs (LNA#A for agile) when they operate under nominal low-noise mode (featuring lower IP1dB) or under nominal high-linearity mode (at the price of a degraded noise figure NF50). This original LNA#A is compared to a robust conventional design using a larger sized device (LNA#R for robust). The step-stresses are operated at 10 GHz, which is the center frequency band of these LNAs. All modes of operation are shown to exhibit fairly reproducible step stress plots, although thermal or nonlinear effects can be differentiated between low-noise and high-linearity operating conditions, and compared with the robust design LNA#R. We demonstrate the relevance of an alternative approach to conventional LNA circuit design strategies in order to achieve natural electronic protection, without a limiter placed before the LNA#A or LNA#R or without turning-off the DC-biasing: this protection option benefits from maintaining the LNA in an operational detection situation for longer when the incident input signal increases, without any degradation in electrical performance (DC and RF) or noise (NF50), even after many sequences of RF step stress.

High-Frequency Performance Study of CNTFET-Based Amplifiers

This article details the design of single- and double-stage maximum gain and low-noise high-frequency amplifiers at 2.4 GHz using a compact carbon nanotube field-effect transistor model, which is initially calibrated with hysteresis-free experimental data from a technology suitable for high-frequency applications. Parameters of the compact model represent CNTFETs with maximum high-frequency gain and reduced high-frequency noise by eliminating the metallic tubes contribution. Studies on linearity of the amplifiers as well as the impact of the quality factor of the inductors used in the stabilization network and the density of the nanotubes on amplifier performance are presented. Results of RF amplifiers show that CNTFETs are credible contenders for developing applications in S-band because of their gain (around 12 dB for a double-stage gain design), low noise ( $NF_{\rm {min}}$ = 1.5 dB for a single-stage LNA) and linearity performance (OIP $_{3}$ around 15 dBm for a single-stage gain amplifier design).

Highly linear dual capacitive feedback LNA for L-band atmospheric radars

This paper presents the design of ultra-low noise amplifier (LNA) with dual capacitive shunt feedback in conjunction with source degenerated inductance methodology to simultaneously improve gain, noise figure (NF), and linearity. Addition of two feedback capacitors from drain to gate of the two transistors will relieve the trade-off between NF and linearity and the cascode design will increase the gain. To demonstrate this methodology, a single stage LNA is designed for UHF atmospheric radar application at 1.3 GHz and pHEMT technology is used for the design of LNA and fabricated on low-loss dielectric substrate. Measured results show that LNA has a gain of 24.1 dB and a very low NF of 0.38 dB. The input and output return losses are less than 11 dB and the third-order input intercept point is 48 dBm.

Compact modelling of InAlN/GaN HEMT for low noise applications

This paper presents results of high-frequency noise modelling of InAlN/GaN high electron mobility transistors (HEMTs) with different formulations of the minimum noise figure NFmin. Current–voltage characteristics and s-parameters of 0.15 μm gate length and 2 × 75 μm gate width InAlN/GaN HEMTs were measured at room temperature in a wide frequency range (300 MHz to 50 GHz) and bias range (VGS from −4.8 to 1 V and VDS from 0 to 21 V). Both the EEHEMT1 and Angelov GaN compact models yielded excellent agreement for transfer and output characteristics, transconductance gm, and fT, fmax. High-frequency noise parameters NFmin, Rn, ΓOPT of InAlN/GaN HEMT were measured in 8–50 GHz frequency band. Noise formulation within the EEHEMT1 model underestimates the measured NFmin and Rn. The well known three-parameter PRC noise model is in a better agreement with the measured data but neglects the shot noise resulting from the gate leakage. The inductive degenerated source matching method and EEHEMT1 were used to design a single stage LNA operated at 8 GHz frequency. A 10 dB gain with an input reflection of −12 dB with a 2.5 dB of noise factor were obtained at 8 GHz.

A 60 GHz receiver front-end in 65 nm CMOS

In the past few years, the mm-wave silicon, especially 60 GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. This paper presents the design of a 60 GHz receiver front-end using 65 nm CMOS technology. Initially, a heterodyne receiver front-end architecture is presented to exploit its possible compatibility with legacy systems. In order to implement the front-end, an EM simulation based methodology and the corresponding design flow are proposed. A transistor EM model, using existing compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on S-parameter data from EM simulation is also derived. After the device modeling efforts, a single-stage LNA and a single-gate mixer are designed using 65 nm CMOS technology. They are characterized by EM co-simulation, and compared with the state-of-the-art. After integration, the simulated front-end achieves a conversion gain of 11.9 dB and an overall SSB noise figure of 8.2 dB, with an input return loss of ?13.7 dB. It consumes 6.1 mW DC power, and its layout occupies a die area of 0.33 mm × 0.44 mm.