Single-stage Distributed Amplifier Research Articles

A 130 nm-SiGe-BiCMOS Low-Power Receiver Based on Distributed Amplifier Techniques for Broadband Applications From 140 GHz to 200 GHz

This work presents a direct-conversion receiver for G-band applications formed by a cascaded single-stage distributed amplifier optimized for low noise, a single-balanced active mixer with inductive peaking and broadband RF matching, and a local oscillator (LO) driver. The receiver is optimized for reduced DC and LO power consumption, while practical levels of linearity and noise are retained. The complete receiver and of the stand-alone mixer are implemented in 0.62 mm2 and 0.39 mm2 of a 130 nm SiGe BiCMOS technology with 450 GHz maximum-oscillation frequency. The measured receiver saturated gain in LO compression is 17 dB with a 6 dB band of 60 GHz and a 3 dB band of 30 GHz, while the input power which compresses the gain by 1 dB ( $\text{P}_{in1dB}$ ) is −35 dBm. The simulated receiver double-sideband noise figure is 11 dB. Finally, the circuit requires an LO power of −17 dBm at 170 GHz and a DC power of 98 mW. The measured gain of the mixer is −13 dB with a 3 dB band of 70 GHz. The component $\text{P}_{in1dB}$ is −20 dBm for −18 dBm LO power and 53 mW DC power. These circuits offer one of the largest operation bandwidth together with one of the lowest DC and LO power consumption against the state of the art.

A 3.7–43.7-GHz Low-Power Consumption Variable Gain Distributed Amplifier in 90-nm CMOS

A variable gain distributed amplifier (VGDA) for the Rx path of ultrawideband phased-array system is implemented in 90-nm CMOS process and presented in this letter. In order to achieve high gain and wideband with relative low dc power dissipation (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> ), the combination of the conventional distributed amplifier (CDA) and the cascaded single-stage distributed amplifier (CSSDA) is utilized to the circuit. Moreover, the active variable termination resistor (AVTR) is adopted to adjust the flatness of gain. According to the experimental results, the proposed VGDA achieves a 21-dB peak gain with a 40-GHz 3-dB bandwidth (3.7-43.7 GHz), 18-dB gain control range (GCR), and 16° maximum phase variation.

InP DHBT Single-Stage and Multiplicative Distributed Amplifiers for Ultra- Wideband Amplification

This paper highlights the gain-bandwidth merit of the single stage distributed amplifier (SSDA) and its derivative multiplicative amplifier topologies (i.e. the cascaded SSDA (C-SSDA) and the matrix SSDA (M-SSDA)), for ultra-wideband amplification. Two new monolithic microwave integrated circuit (MMIC) amplifiers are presented: an SSDA MMIC with 7.1dB average gain and 200GHz bandwidth; and the world's first M-SSDA, which has a 12dB average gain and 170GHz bandwidth. Both amplifiers are based on an Indium Phosphide DHBT process with 250nm emitter width. To the authors best knowledge, the SSDA has the widest bandwidth for any single stage amplifier reported to date. Furthermore, the three tier M-SSDA has the highest bandwidth and gain-bandwidth product for any matrix amplifier reported to date.

Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS

This paper describes a novel distributed amplifier (DA) architecture for ultra-wide band of operation at millimeter-wave frequency. The DA consists of two cascaded single-stage DAs (CSSDAs) embedded in a balanced architecture. The implemented design retains the benefits of CSSDAs in terms of high maximum frequency, broad band of operation, and compact area, while significantly improving the amplifier input and output matching and its linearity with the balanced architecture, which are the major issues of this class of circuits. The small-signal analysis is provided in detail and explains the nature of the poor output matching typical of this class of DAs. Furthermore, the CSSDA gain is calculated as function of frequency and circuit parameters, extending available literature results, and providing direct design guidelines with a compact formula. Experimental validation is demonstrated with the fabrication of a circuit prototype in a 130-nm SiGe BiCMOS process. The circuit is able to provide an average of 16-dB gain over the frequency band 30–220 GHz, with input- and output-return losses above 10 dB, and a maximum measured output-referred 1-dB compression point of 4.5 dBm. To the best knowledge of the authors, the measured matching and linearity are the best reported for CSSDAs.

Analysis and Design of a 220-GHz Wideband SiGe BiCMOS Distributed Active Combiner

This paper presents the first active power combiner designed for ultrawideband applications covering a bandwidth of operation from 1 to 220 GHz. The circuit is implemented in a high-performance 0.13- $\mu \text{m}$ SiGe BiCMOS technology ( $f_{\mathrm { {max}}} = 450$ GHz) and based on an innovative dual-stage distributed architecture. The input stage realizes the power combination with a traveling-wave architecture. The output stage is a cascaded single-stage distributed amplifier, and it is employed to increase the overall gain. The circuit analysis necessary for circuit design is given, and its predictions are compared with the measurements in the time and frequency domains. The system requires 203 mW of dc power to provide a signal amplification of 20 dB from 1 to 170 GHz, which decreases to 15 dB at 220 GHz. Independent bias networks for the combining paths also enable a gain tuning range of 20 dB. The presented circuit improves by a factor 16 the state of the art for frequency of operation of distributed power combiners implemented in silicon and by a factor 20 the bandwidth. Compared with III–V implementations, the improvement factors are 4.5 and 5.5, respectively.

A novel design of ultra-broadband, high-gain and high-linearity variable gain distributed amplifier in 0.13 μm CMOS technology

ABSTRACTA high-gain, high-linearity and ultra-broadband variable gain distributed amplifier (VGDA) based on employing multiple techniques is presented to substantially increase the gain. The complete design is composed of two major parts including a VGDA part followed by a single stage distributed amplifier (SSDA) part. The VGDA part makes it possible to achieve different gain settings. For high gain considerations, the SSDA part cascades with the VGDA part that takes the benefits of the multiplicative gain mechanism. A theory is presented to enhance the linearity without imposing further DC power consumption. This idea has been validated by simulation results as expected. The design is analysed and simulated in the standard 0.13 μm CMOS technology. It presents the large gain tuning range of 35 dB, from –5 dB attenuation gain up to +30 dB maximum amplification gain, in relation to the control voltage (Vctr) that varies between 0.42 and 1.1 V. At the maximum amplification gain setting, it presents a DC up to 16 GHz 3 dB bandwidth, an average noise figure of 3.2 dB and an IIP3 of –2 dB m. Furthermore, it dissipates 46.42 mW from 0.7 and 0.9 V power supplies of the drain lines of VGDA and SSDA parts, respectively. Additionally, the Monte Carlo (MC) simulation has been performed to predict an estimate of the accuracy of performance of the proposed design under various conditions.

InP DHBT Distributed Amplifiers With Up to 235-GHz Bandwidth

Three wideband amplifiers in double-heterojunction bipolar transistor technology have been designed and measured. The amplifiers use different types of distributed amplifier (DA) topologies, all based on cascode gain cells. A single-stage DA design achieves 7.5-dB gain and 192-GHz bandwidth and a two-cascaded single-stage DA achieves an average gain of 16 dB with a bandwidth of 235 GHz. The third circuit is a conventional DA with more than 10-dB gain from 70 kHz up to 180 GHz. To the authors’ best knowledge, the single-stage DA and the two-cascaded single-stage DA are the widest band amplifiers in any technology reported to date. Furthermore, the conventional DA has a record bandwidth for circuits in conventional DA topology with gain from near dc.

Wideband active quasi‐circulator with tunable isolation enhancement

An active quasi-circulator comprises three single-stage distributed amplifiers (DAs), in which two are for wideband transmission while the remaining one is for wideband signal cancellation. This quasi-circulator has wideband frequency operation and by optimising the bias current, tunable isolation enhancement between port 1 and port 3 is achieved. The experimental results show that this quasi-circulator has insertion losses of around 0 dB, return losses better than 10 dB at each port, minimum non-tunable isolation of around 15 dB from 0.8 to 2.2 GHz and tunable isolation of more than 40 dB between port 1 and port 3 from 0.8 to 2.2 GHz.

A Novel Distributed Amplifier With High Gain, Low Noise, and High Output Power in ${\hbox{0.18-}} \mu{\hbox {m}}$ CMOS Technology

A new distributed amplifier (DA) topology is proposed, which is a combination of the conventional DA and the cascaded single-stage DA. This DA topology can provide wide bandwidth with considerations of the gain, noise figure (NF), and output power simultaneously, and requires reasonable dc power consumption. In this paper, two termination methods of this combination are investigated. From the measurements, the first DA proposed by Chen in 2011 has a small-signal gain of 20.5 dB, a 3-dB bandwidth of 35 GHz, and a gain-bandwidth (GBW) product of 371 GHz. The maximum output power at 1-dB output compression point $(OP_{1~{\rm {dB}}})$ is 8.6 dBm and the NF is between 6.8–8 dB at frequencies lower than 18 GHz. The chip size, including testing pads, is only ${\hbox {0.78 mm}}^{2}$ , and the ratio of the GBW to chip size is ${\hbox{476 GHz/mm}}^{2}$ . The second DA has a small-signal gain of 24 dB, a 3-dB bandwidth of 33 GHz, and a GBW product of 523 GHz. The maximum $OP_{1~{\rm {dB}}}$ is 9 dBm and the NF is between 6.5–7.5 dB at frequencies lower than 18 GHz. The chip size including testing pads is only ${\hbox {0.83 mm}}^{2}$ , and the ratio of the GBW to chip size is ${\hbox{630 GHz}}/{\hbox {mm}}^{2}$ . To the authors' knowledge, the second circuit has the highest ratio of GBW to chip area and the highest figure-of-merit in ${\hbox{0.18-}} \mu{\hbox {m}}$ CMOS, and it has a comparable performance with other DAs in advanced process.

Cascaded single-stage distributed amplifier using DPHEMT devices for multioctave performance

This paper describes a multioctave (2---18 GHz) distributed amplifier design using the concept of cascaded reactively terminated single-stage distributed amplifier (CRTSSDA) configuration for EW applications. The concept of CRTSSDA is demonstrated to provide broadband performance with high gain, reduced power consumption, circuit stability and superior power-added efficiency compared to conventional distributed amplifiers using the same number of active devices. The broadband amplifier employing three-CRTSSDA is designed and fabricated using three different DPHEMT devices in the three respective stages of the design to further enhance the amplifier's efficiency performance. The amplifier achieved an associated gain level above 26 dB with flatness of <± 0.5 dB, an average power-added efficiency in access of 27% at an output power of 25 dBm across 2---18 GHz with an efficiency peak of 30% at 12 GHz. The input and output VSWR of better than 2:1 was achieved. Furthermore, the CRTSSDA provides a cost-effective solution when compared to the conventional travelling wave amplifier as only half the number of active devices is used. Fabrication of the amplifier was carried out by using the conventional thin-film microwave integrated circuit technology. The CRTSSDA is also disposed to realization by monolithic circuit technology.

Broad-band MMICs based on modified loss-compensation method using 0.35-/spl mu/m SiGe BiCMOS technology

Using the concept of loss compensation, novel broad-band monolithic microwave integrated circuits (MMICs), including an amplifier and an analog multiplier/mixer, with LC ladder matching networks in a commercial 0.35-/spl mu/m SiGe BiCMOS technology are demonstrated for the first time. An HBT two-stage cascade single-stage distributed amplifier (2-CSSDA) using the modified loss-compensation technique is presented. It demonstrates a small-signal gain of better than 15 dB from dc to 28 GHz (gain-bandwidth product=157 GHz) with a low power consumption of 48 mW and a miniature chip size of 0.63 mm/sup 2/ including testing pads. The gain-bandwidth product of the modified loss-compensated CSSDA is improved approximately 68% compared with the conventional attenuation-compensation technique. The wide-band amplifier achieves a high gain-bandwidth product with the lowest power consumption and smallest chip size. The broad-band mixer designed using a Gilbert cell with the modified loss-compensation technique achieves a measured power conversion gain of 19 dB with a 3-dB bandwidth from 0.1 to 23 GHz, which is the highest gain-bandwidth product of operation among previously reported MMIC mixers. As an analog multiplier, the measured sensitivity is better than 3000 V/W from 0.1 to 25 GHz, and the measured low-frequency noise floor and corner frequency can be estimated to be 20 nV/sqrt(Hz) and 1.2 kHz, respectively. The mixer performance represents state-of-the-art result of the MMIC broad-band mixers using commercial silicon-based technologies.

Improving the Gain-Frequency Performance of Cascaded Single-Stage Distributed Amplifiers with Bandpass Filter Structure

In this paper a bandpass filter structure is proposed for realizing the artificial transmission lines of cascaded single-stage distributed amplifiers (CSSDA) and the basic analysis and design of the bandpass structured CSSDA (BP-CSSDA) is demonstrated. Some of the lower frequency region in the gain-frequency band of the CSSDA is not utilized due to presence of the bias components in traditional design methods. By using the bandpass structure for the realization of artificial transmission lines, the unused portion of the gain-frequency band can be utilized. Therefore, one can obtain more bandwidth using the bandpass type artificial lines in the CSSDA than using the lowpass type lines. The gain of a CSSDA can be increased, by increasing the interstage termination impedance (Z0int) without compromising the bandwidth. In this paper, a graphical method for determining the optimum Z0int is introduced. Simulation results showing the advantage of using the BP structured artificial lines in the CSSDA is provided.

Design and analysis of novel high-gain and broad-band GaAs pHEMT MMIC distributed amplifiers with traveling-wave gain stages

Using the concept of traveling-wave gain stages, novel GaAs pseudomorphic high electron-mobility transistor monolithic-microwave integrated-circuit (MMIC) distributed amplifiers (DAs) are demonstrated to achieve high gain and over several octaves of bandwidth performance simultaneously for microwave and millimeter-wave frequency applications. The cascaded single-stage distributed amplifier (CSSDA) is used as traveling-wave gain stages to improve the gain performance of the conventional distributed amplifier (CDA). By adopting the low-pass filter topology between the CDA and CSSDA and tuning the gain shape of CDA and CSSDA separately, a broad-band and high-gain DA, called CDA-CSSDA-2, was accomplished. The detailed design equations are derived for the broad-band matching design of this CDA-CSSDA-2. Two other MMICs, namely, a two-stage CSSDA called 2-CSSDA, and another two-stage design called CDA-CSSDA-1, are also included in this paper. This CDA-CSSDA-2 achieves 22/spl plusmn/1.5-dB small-signal gain from 0.1 to 40 GHz with a chip size of 1.5/spl times/2 mm/sup 2/. It also produces a gain-bandwidth product of 503 GHz, which is the highest among all reported GaAs-based DAs. The flat group delay also demonstrates the feasibility of this design for future digital optical communications and broad-band pulse applications.

A filter synthesis technique applied to the design of multistage broad-band microwave amplifiers

A method for designing multistage broad-band amplifiers based upon well-known filter synthesis techniques is presented. Common all-pole low-pass approximations are used to synthesize prototype amplifier circuits that may be scaled in frequency and impedance. All-pass filters introduced at the first stage are shown to improve input match while maintaining circuit performance less 6 dB gain. A theoretical comparison is made with the distributed amplifier and the cascaded single-stage distributed amplifier. Theoretically, a larger gain-bandwidth product is achieved using the synthesis technique. A proof-of-concept Butterworth low-pass two-stage amplifier was designed, simulated, and measured and achieved a flat gain performance of 1-4 GHz with a power gain of 14.5/spl plusmn/1 dB close to the predicted 1-4.2 GHz, 15/spl plusmn/1 dB.

Broadband amplification in CMOS technology using cascaded single-stage distributed amplifier

Feasibility of the cascaded single-stage distributed amplifier (CSDA) for ultra broadband amplification in complementary metal-oxide-semiconductor (CMOS) technology is investigated. A number of unique benefits gained from the CMOS CSDA over the conventional CMOS distributed amplifier structure are highlighted along with bandwidth analysis and helpful consideration. Simulated in the standard digital 0.35 µm CMOS process with realistic parasitic models, a prototype design of a four-stage CMOS CSDA provides 21 dB power gain at 5 GHz bandwidth, better than −10 dB input/output return loss and dissipates &lt;132 mW.

Experimental performance of ultra-broadband amplifier design concept employing cascaded reactively terminated single-stage distributed amplifier configuration

Experimental results of a novel ultra-broadband amplifier operating over the frequency range of 2–18 GHz are presented. The amplifier comprises a cascaded reactively terminated single-stage distributed amplifier (CRTSSDA) configuration. The amplifier employs double heterojunction pseudomorphic high electron mobility transistors (DPHEMTs). The fabricated CRTSSDA is shown to exhibit higher gain, reduced power consumption, and a superior efficiency performance compared to the equivalent gain conventional travelling amplifier design approach.

Analysis of the performance of four-cascaded single-stage distributed amplifiers

In this paper, the analysis, design, and implementation of a hybrid broad-band distributed amplifier based on four-cascaded single-stage distributed amplifiers (4-CSSDAs) is demonstrated. The available gain produced by this amplifier is significantly higher than conventional distributed amplifiers (CDAs) using the same number of active devices. Simulation results for two versions of the 4-CSSDA are demonstrated, one with low interstage characteristic impedance (Zo/sub int/) and the other with high Zo/sub int/. Simulation results show a number of advantages of the proposed amplifier over the CDA, in particular, that the available gain can be increased by increasing the Zo/sub int/ of the amplifier stages. Simulation predicts that gains approaching 50 dB could be achieved by appropriate design modification. Measured results for implementation of the two versions of the 4-CSSDA are reported. These show excellent performance with high gain, good gain flatness, input and output matching, flat group delays, and a low noise figure across a 1-10-GHz bandwidth. The amplifier configuration achieved a measured wide-band performance (0.8-10.8 GHz) with up to 39/spl plusmn/2-dB flat gain using discrete packaged active devices.