Single-poly EEPROM Research Articles

A single-poly EEPROM with low leakage charge pump and peripheral circuits for passive RFID tag in a standard CMOS technology

A single-poly EEPROM with low leakage charge pump and peripheral circuits for passive RFID tag in a standard CMOS technology

Design of 512-bit logic process-based single poly EEPROM IP

A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18 μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 μW, respectively, and the EEPROM size is 0.12 mm2.

A control-gate-assisted erasing method for a single-poly EEPROM cell with metallic control gate structure

A control-gate- (CG) assisted erasing method is investigated for the embedded single-poly EEPROM cell with metallic CG structure. Without the CG bias polarity limitation, which suffers in the diffused n-well CG EEPROM cells, the metallic CG cells can apply negative voltage at CG. By negatively biasing the CG, an enhanced electric field, and thus an improved erasing speed can be achieved for the source erasing. With the channel hot electron (CHE) programming and the enhanced erasing method, an enlarged threshold window can be obtained. In addition, the reliability of the EEPROM cell fabricated with the foundry standard CMOS process with an enhanced erasing method is studied.

A single-poly EEPROM cell for embedded memory applications

We present a novel single-poly-silicon EEPROM cell for embedded memory. The cell is integrated in a 0.13μm RF-CMOS technology without process modifications and is composed of an NMOS transistor and a MOS capacitor on two isolated P-wells sharing a floating poly-silicon layer. A two-polarity voltage of ±6V is applied for writing and erasing using uniform-channel Fowler–Nordheim tunnelling. Operations faster than 1ms, endurance over 10+3 cycles and data retention longer than 10 years are demonstrated.

Single poly-EEPROM with stacked MIM and n -well capacitor

The new structure of electrically erasable programmable read-only memory (EEPROM), using a capacitor of stacked metal-insulator-metal (MIM) and n-well, is proposed. The oxide capacitance in the n-well region is effectively applied without sacrificing the cell area and the control gate coupling ratio. Therefore, for the same program-voltage rating, the proposed cell allows the EEPROM to have a higher speed handling capability even with a quite small cell size. Measured results show that the programming speed of the proposed cell is almost the same as that of the conventional MIM control gate cell. In an endurance test of 10 000 program/erase cycles, the shift of program threshold voltage is found to be 1.4 V without degradation of read currents.

A single-poly EEPROM cell structure compatible to standard CMOS process

A novel cell structure is proposed for low cost, low capacity EEPROMs. The cell is composed of an NMOSFET and a MOS capacitor with a shared poly-silicon layer that functions as the floating gate of the cell. This nonvolatile cell can be fabricated by a standard CMOS process technology without any extra steps. Detailed analyses are carried out for the dependence of the performance on the capacitance ratios C C/ C D between the NMOSFET C D and the MOS capacitor C C. The efficiencies of program/erase operations, the ability of data retention and the cyclic endurance are also discussed.

Novel single-poly EEPROM with damascene control-gate structure

A novel single-poly EEPROM using damascene control gate (CG) structure is presented in this letter. The CG is tungsten (W) line made by a damascene process, and intergate dielectric is Al/sub 2/O/sub 3/ grown by atomic layer deposition (ALD). The program and erase mechanism is the same as the one for traditional stacked-gate cell, which uses the channel hot electron injection for programming and Fowler-Nordheim tunneling for channel erasing. With the high dielectric constant (K) property of Al/sub 2/O/sub 3/, we can perform the program and erase function with a voltage less than 6.5 V, which can be handled by 3.3 V devices instead of traditional high voltage devices. In the process compatibility aspect, this new cell needs only two extra masking steps over the standard CMOS process, and the high-/spl kappa/ material is deposited in the back-end metallization steps without the contamination concerns on the front-end process. Therefore, this new technology is suitable for embedded application. In this letter, the good cell performance is demonstrated; such as, fast programming/erasing, good endurance and data retention.

A 1-Kbit EEPROM in SIMOX technology for high-temperature applications up to 250/spl deg/C

A 1-Kbit high-temperature EEPROM memory module has been developed in a 1.6-/spl mu/m thin-film SIMOX technology. The memory array is based on single-poly EEPROM cells, which are erased and programmed by Fowler-Nordheim tunneling. Operation at elevated temperatures is achieved by a special array design, suitable for elimination of cell-disturb problems caused by temperature-induced leakage currents of the select transistors. High-voltage switching is done without PMOS transistors in order to avoid leakage currents due to the backgate effect. The memory module is designed for 5-V only operation and offers an access time of 260 ns at an operating temperature of 250/spl deg/C. At 250/spl deg/C, data retention of 3000 h and an endurance of 10000 erase/program cycles has been achieved. The area of the 1-Kbit memory module is 0.89/spl times/2.71 mm/sup 2/.

A single-poly EEPROM cell in SIMOX technology for high-temperature applications up to 250/spl deg/C

A thin-film SIMOX technology has been used for fabrication of a single-polysilicon EEPROM cell suitable for high-temperature applications. The two transistor cell is composed of a select transistor and a floating gate transistor with 10 nm tunnel oxide. The EEPROM process extension requires only a few steps suitable for embedded memory applications with low cost and turn around time. Endurance and data retention characteristics of the SIMOX EEPROM cell are presented for a temperature of 250/spl deg/C. The problem of temperature induced leakage currents in the select transistor at elevated temperatures is investigated.

A scalable single poly EEPROM cell for embedded memory applications

An increasing number of integrated circuits requires the embedding of a limited amount (up to 16–64 kbits) of EEPROM memory. For this application, low process complexity, robust structure and good reliability are more important than small cell size. In this paper we present the design and characterization of a single poly EEPROM cell, optimized for embedded applications, and characterized by a good shrink potential. A. cell area of 68.7 μ 2 has been obtained in 0.7 μm technology, and electrical characterization has shown the possibility of achieving a programming time of less than 1 msec, while an endurance of more than 10 million cycles has been achieved at 125°C, with a programming time of 2 msec. By further shrink of the same basic layout, cell areas of 55 and 44μm 2 have been obtained, and similar programming and endurance performances have been demonstrated.

A single poly EEPROM cell structure for use in standard CMOS processes

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a "floating gate". The inversion layer as "control node (gate)". Test chips which were fabricated in a 0.8 /spl mu/m/150 /spl Aring/ standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>