Single-phase Seven-level Inverter Research Articles

Genetic Algorithm Based 7-Level Step-Up Inverter with Reduced Harmonics and Switching Devices

This paper presents a unique voltage-raising topology for a single-phase seven-level inverter with triple output voltage gain using single input source and two switched capacitors. The output voltage has been boosted up to three times the value of input voltage by configuring the switched capacitors in series and parallel combinations which eliminates the use of additional step-up converters and transformers. The selective harmonic elimination (SHE) approach is used to remove the lower-order harmonics. The optimal switching angles for SHE is determined using the genetic algorithm. These switching angles are combined with a level-shifted pulse width modulation (PWM) technique for pulse generation, resulting in reduced total harmonic distortion (THD). A detailed comparison has been made against other relevant seven-level inverter topologies in terms of the number of switches, drivers, diodes, capacitors, and boosting facilities to emphasize the benefits of the proposed model. The proposed topology is simulated using MATLAB/SIMULINK and an experimental prototype has been developed to validate the results. The Digital Signal Processing (DSP) TMS320F2812 board is used to generate the switching pulses for the proposed technique and the experimental results concur with the simulated model outputs.

A new boost type single source seven-level switched-capacitor based inverter with reduced current stress over the components

This paper proposes a new single-phase seven-level inverter. The proposed multilevel inverter is based on a Switch-Capacitor (SC) cell and it has the capability to boost the output voltage. This achievement is obtained by a single input voltage source. The main shortcoming of SC networks is the inrush currents passing through the capacitors while being charged. The proposed multilevel inverter overcomes this problem by using a charging-inductor that charges the utilized capacitor smoothly. The performance of the proposed multilevel inverter is described in different operational modes. The power losses of the used components are analyzed. Design guidance to find optimal values of passive components is given. Comparison is also performed between the proposed multilevel inverter and several conventional seven-level inverters. The proposed multilevel inverter is simulated in MATLAB/Simulink environment under grid-tied transformer-less operation. The experimental 210 VA prototype confirms the correctness of the given theories and the correct operation of the proposed topology.

Low-Voltage Stress Seven-Level Inverter Based on Symmetrical Capacitors

A step-up single-phase seven-level inverter is proposed in this article. The proposed multilevel inverter (MLI) uses one voltage source and two symmetrical capacitors. Two capacitors are provided with self-voltage balancing ability, eliminating the requirement for sensors or additional control loop. The proposed topology generates bipolar levels inherently without the use of inverting H-bridge, so that the total standing voltage of switches is greatly reduced. The blocking voltages of all the switches are limited to the input voltage, and thus the proposed topology has low-voltage stress. Furthermore, the proposed structure has the advantages of voltage-boosting capability and high efficiency. The maximum output voltage is 1.5 times the input voltage. The prominent merits make it suitable for distributed generation applications. In this article, the circuit configuration of the proposed topology, operation principle, and the phase disposition pulsewidth modulation (PD PWM) strategy are presented. Furthermore, the mathematical calculations of power loss and parameter comparisons are performed to demonstrate the superiority. Finally, the experimental results are presented to verify the feasibility of the proposed topology.

A cascaded converter using hybrid cells and H-bridge structure

This paper introduces a cascaded converter structure using hybrid two-level cells to form a single-phase seven-level inverter. Compared to various conventional and existing multilevel (MLI) topologies, this topology requires a lower number of devices. It uses several DC sources integrated in two-stage cells to provide the required voltage. In this topology, the DC-link condensers are not necessary. The modes of operation and modulation of the structure proposed are described in depth. Finally, in the MATLAB/Simulink platform the new topology is evaluated and the results reported.

Analysis and simulation of a single-phase seven-level inverter controlled by modified sinusoidal PWM technique

In this paper, a modified sinusoidal pulse width modulation (MSPWM) technique and a modified single-phase H-bridge seven-level inverter is proposed. The switching pulses for the proposed seven-level inverter are generated using a single triangular carrier waveform, a fully rectified sinusoidal signal, and three stepped reference signals (Uref1, Uref2 and Uref3). Using optimization technique, the magnitude of the stepped reference signal is determined so that the total harmonic distortion (THD) of the output voltage waveform is minimum and the fundamental component, RMS value of the voltage is improved for a given modulation index Ma as compared to the sinusoidal pulse width modulation (SPWM). By the implementation of the new scheme, the seven-level of the inverter output voltage level (+Vdc, +2Vdc/3, +Vdc/3, 0, −Vdc, −2Vdc/3, −Vdc) is obtained for any given modulation index. Similarly, if only two stepped reference signals are used then the inverter will act as a five-level inverter for any modulating index Ma. The proposed MSPWM and seven-level inverter are simulated on MATLAB/SIMULINK for R, R-L load and on a single-phase capacitor-start and capacitor-start-run Induction Motor.

Asynchronous Particle Swarm Optimization-Genetic Algorithm (APSO-GA) Based Selective Harmonic Elimination in a Cascaded H-Bridge Multilevel Inverter

In this article, a hybrid asynchronous particle swarm optimization-genetic algorithm (APSO-GA) is proposed for the removal of unwanted lower order harmonics in the cascaded H-bridge multilevel inverter (MLI). The APSO-GA is applicable to all levels of MLI. In the proposed method, ring topology based APSO is hybrid with GA. APSO is applied for exploration and GA is used for the exploitation of the best solutions. In this article, optimized switching angles are calculated using APSO-GA for seven-level and nine-level inverter, and results are compared with GA, PSO, APSO, bee algorithm (BA), differential evolution (DE), synchronous PSO, and teaching–learning-based optimization (TLBO). Simulation results show that APSO-GA can easily find feasible solutions particularly when the number of switching angles is high; however, the rest of all stuck at local minima due to less exploration capability. Also, the APSO-GA is less computational complex than GA, BA, TLBO, and DE algorithms. Experimentally, the performance of APSO-GA is validated on a single-phase seven-level inverter.

Investigation of different MPPT techniques based on fuzzy logic controller for multilevel DC link inverter to solve the partial shading

Generally, partially shaded conditions frequently arise in large photovoltaic generation systems which in turn cause system losses. Therefore, arrival of multiple peak values is possible in the power–voltage characteristic curves of photovoltaic systems. Such kind of issues is resolved through the usage of novel control algorithms for multilevel dc link inverters. These algorithms depend on the arrangement of pulse width modulation and direct pulse width modulation system to be with MPPT performance based on fuzzy controller to control the multilevel DC link inverter. Under the partial shading conditions, the proposed algorithm is applied on single-phase seven-level inverter with isolated maximum power point tracking techniques. The maximum power recovery of photovoltaic sources is enabled by several maximum power point tracking (MPPT) techniques like modified perturb and observe (P&O), incremental conductance and voltage hold P&O. The spectral quality of the inverter output is observed through the simulation studies of MATLAB/Simulink working platform. Also, hardware results are verified with the help of ATMEGA8 microcontroller.

A Novel Reduced Components Model Predictive Controlled Multilevel Inverter for Grid-Tied Applications

This paper presents an improved single-phase Multilevel Inverter (MLI) which is conceptualized to reduce power switches along with separate DC voltage sources. Compared with recent modular topologies, the proposed MLI employs a reduced number of components. The proposed inverter consists of a combination of two circuits, i.e., the level generation and polarity generation parts. The level generation part is used to synthesize different output voltage levels, while the polarity inversion is performed by a~conventional H-bridge circuit. The performance of the proposed topology has been studied using s single-phase seven-level inverter, which utilizes seven power switches and three independent DC voltage sources. Model Predictive Control (MPC) is applied to inject a sinusoidal current into the utility grid which exhibits low Total Harmonic Distortion (THD). Tests, including a~change in grid current amplitude as well as operation under variation in Power Factor (PF), have been performed to validate the good performance obtained using MPC. The effectiveness of the proposed seven-level inverter has been verified theoretically using MATLAB Simulink. In addition, Real-Time (RT) validation using the dSPACE-CP1103 has been performed to confirm the system performance and system operation using digital platforms. Simulation and RT results show improved THD at 1.23% of injected current.

A New Space Vector Pulse Width Modulation Technique for Single-Phase Seven-Level Inverter with Reduced Number of Switches

ABSTRACTSpace vector pulse width modulation is an advanced modulation algorithm which offers many advantages over the sinusoidal pulse width modulation technique. Space vector pulse width modulation is a well-researched topic for three-phase inverters, but only a very few works have been reported in the literature on the application of the space vector pulse width modulation technique for single-phase inverters. Conventional space vector pulse width modulation algorithms for single-phase inverters have concentrated mainly on two-level inverters where the reference vector falls only in two sectors. But for single-phase multilevel inverters, the switching patterns in different sectors are to be properly controlled for generating the desired number of levels. This paper proposes a new space vector pulse width modulation algorithm for single-phase multilevel inverter which incorporates an efficient algorithm for the proper selection of switches in different sectors to get the desired number of levels in the output voltage. The proposed algorithm is implemented on a simplified seven-level inverter which uses fewer numbers of switches in comparison with the conventional cascaded multilevel converter. The validity of the suggested space vector pulse width modulation technique is verified through simulations and experiments.

Normally Bypassed Cascaded Sources Multilevel Inverter with RGA Optimization for Reduced Output Distortion and Formulaic Passive Filter Design

The distributed generation involving multiple photovoltaic sources and synthesizing high-quality ac voltage from those multiple dc sources are nascent research ambits. A host of multilevel inverters (MLIs) has been ascertained for performing above errand diligently, where the component count is obnoxious. The single phase seven-level inverter is an acquiescent compromise between the circuit complexity and the quality of the output. Further enhancement on the performance can be succored through optimizing dc link voltages and switching angles. This paper proposes a component count pruned MLI structure and also a refined genetic algorithm (RGA)-based optimization scheme for the computation of both dc link voltages and switching angles. Previous attempts for this problem have solved the switching angles with the objective of resulting minimum harmonic content in the staircase-shaped output voltage. The dc link voltage of each level is however assumed to be the same and constant. As an extension, RGA-based optimization of both dc link voltages and switching angles is triumphed. The harmonic profile of the proposed switching strategy is simulated and also corroborated by a hardware prototype. In practice, the proposed fundamental switched strategy is apposite, in which each dc voltage can be self-maintained and independently controlled. In addition, a method for designing the passive LC filter is also presented.

Design and Implementation of a New Multilevel Inverter Employing Reduced Components

This paper focuses on an implementation of new topology which can synthe-size multi-level output voltage at the load terminals. The proposed inverter consists of two main parts; level generation part and polarity generation part. Level generation part is responsible for generating voltage levels at its end while; polarity generation part is a traditional H-bridge which is used to provide inversion of the output voltage levels. Single-phase seven-level inverter has been presented from the proposed multilevel inverter. This topology offers reduced number of switching components compared with many recent availa-ble topologies particularly for high number of levels. Due to the multi-level output voltage, low total harmonic distortion (THD), less circuit complexity, less cost and high efficiency can be obtained. A conventional PI controller is used for load voltage regulation to obtain output voltage near to sinusoidal. Computer-aided using the dSPACE_CP1103 controller and experimental setup are carried out to provide the validity and effectiveness of the proposed invert-er.

A Single-Phase Step-Up Seven-Level Inverter With a Simple Implementation Method for Level-Shifted Modulation Schemes

This paper proposed a single-phase seven-level inverter topology with a simple implementation method for level-shifted modulation schemes, which includes two novelty work. One aspect of the work is the proposed inverter topology that integrates a three-time step-up ratio and capacitor voltage self-balance capability. Compared to the existing single-phase seven-level inverters, the proposed inverter reduces the number of power switches and the voltage stresses across them. The other aspect of the work is a new way to implement level-shifted modulation schemes (level-shifted carrier modulation scheme and level-shifted sine modulation scheme) by three basic steps: (1) obtaining modulation logic based on Karnaugh Map technique; (2) determining a level-shifted modulation scheme; and (3) software implementation using the general-purpose input output(GPIO) terminals and CPU timer interruption function of a DSP chip. Therefore, complex trigonometric calculations of the traditional implementation methods for carrier modulation schemes are replaced by simple logic operations of the proposed implementation method, and thus extra logic chips used in the traditional implementation methods are not necessary for the proposed implementation method. Both simulation and experimental results are presented to verify the proposed inverter topology and the proposed implementation method for level-shifted modulation schemes.

Performance Evaluation of SEPIC Based Single-Phase Seven-Level Inverter for Renewable Applications

Contemporary research in multilevel inverters (MLIs) is becoming famous for low power renewable applications. In this paper, therefore, a new configuration of SEPIC based single-phase seven-level inverter is presented with the advantages of lower parts count, size, and reduced cost. The front-end sepic inverter is used to boost the input voltage to the desired voltage and cascaded with a 1:2 multi-winding high-frequency transformer to generate V dc and 2V dc which is fed to the asymmetrical six switch multilevel inverter. The simulation work is carried out in Matlab/Simulink environment, and a laboratory prototype model is developed to validate the concept. The control pulses for the SEPIC inverter is built using TMS3202812 DSP in real time workshop(RTW), and the switching pulses for MLI are generated using a Spartan-6 FPGA Processor. The performance of the proposed topology evolved for the step change in input voltages, and the different loading conditions. A detailed comparison of various seven-level inverter topologies is also conducted.

Modified Cascaded Multi-level Inverter Structure with Reduced Voltage Stress Across H-Bridge for High Voltage Application

This paper presents a modified cascaded multi-level structure for high voltage application. The topology proposed optimizes switch count per voltage level along with the reduction in voltage stress across the switches. Optimization based on different criteria has been discussed and a comparison of the proposed structure with existing topology has been carried out. This paper also shows a level shift PWM control scheme and a closed loop multi-band hysteresis control scheme. The topology is simulated for the above two control schemes on MATLAB and also verified experimentally for single phase seven-level inverter. The experimental verification was done with DSP F28337D TI Launchpad on series resistance and inductance (RL) load.

Asymmetric H-Bridge Single-Phase Seven-Level Inverter Topology with Proportional Resonant Controller

ABSTRACT This paper presents an asymmetrical H-bridge single-phase seven-level inverter topology with modified gating scheme for reducing the number of high-frequency switches. Due to shortcomings like steady-state error and problems in removing low-order harmonics associated with proportional integral controller, proportional resonant controller is used for grid-connected converter current control. A practical application of proportional resonant current controller is developed using a low-cost dsPIC33EP256MC202 microcontroller to keep the current injected in to the grid. The validity of proposed inverter and control scheme is verified through simulation and implemented for low-voltage laboratory prototype.

Design of Single-Phase Seven-Level Grid-Connected Inverter using Solar System

This paper proposes a single phase seven-level inverter for grid-connected photovoltaic system, with a novel pulse width-regulated (PWM) control plan. Three reference signals that are indistinguishable to one another with a balance that is proportionate to the abundancy of the triangular bearer sign were utilized to produce the PWM signals. The inverter is fit for delivering seven levels of output voltage levels (Vdc, 2Vdc/3, Vdc/3, 0, −Vdc, −2Vdc/3, −Vdc/3) from the dc supply voltage. A computerized proportional-integral current-control calculation was executed in a TMS320F2812 DSP to keep the current infused into the grid sinusoidal. The proposed system was confirmed through simulation and implemented in a prototype.

Fuzzy Logic Controlling of a Single Phase Seven-Level GridConnected Inverter for Photovoltaic system

This paper proposes fuzzy logic controller based a single-phase seven-level inverter for grid-connected photovoltaic systems, with a novel pulse width-modulation (PWM) control scheme. Three reference signals produces from fuzzy logic controller which are identical to each other are going to compare with the amplitude of the triangular carrier signal. The inverter is capable of producing seven levels( Vab = Vdc Vab = 2Vdc/3 Vab = Vdc/3 Vab = 0 Vab = −V dc/3 Vab= − 2Vdc/3 Vab = −V dc )of output-voltage levels from the dc supply voltage. The total harmonic distortion is reduces by this control strategy. The proposed system was verified through simulation.

Elimination of Harmonics in Photovoltaic Seven-level Inverter with Newton-raphson Optimization

Abstract This paper describes a strategy to optimize the switching angle of a modified H-bridge single-phase seven-level inverter for stand-alone photovoltaic (PV) system. The inverter comprises a conventional H- bridge inverter and two bidirectional switches. It can generate seven-level output voltage level, namely +Vdc, +2/3Vdc, +1/3Vdc, 0, -1/3Vdc, -2/3Vdc and -Vdc. Optimized Harmonic Elimination Stepped Waveform (OHESW) technique was employed to improve the output waveform quality. Newton- Raphson method is engaged to solve the transcendental equations from OHESW technique which produces all possible solutions with any random initial guess. Among which sets, the one producing the least output-voltage THD was chosen. Computation resulting from the optimized switching angle was simulated. A small-scale laboratory prototype was built and tested. Its results indicated the proposed method's effectiveness and the application feasibility of the fundamental frequency switching.

Multilevel Inverter for Single Phase System with Reduced Number of Switches

Multilevel inverter has emerged recently as a very important alternative in the area of high-power medium voltage energy control. This project present cascaded multi cell with separate DC sources. Multilevel inverters are promising they have nearly sinusoidal output-voltage waveforms, output with better harmonic profile, less stressing of electronic components. The conventional is a single-phase seven-level inverter for grid- connected photovoltaic systems, with a novel pulse width-modulated (PWM) control scheme .In a conventional paper to get the thirteen level inverter output voltage using a six full bridge cascaded type inverter with 24 switches .The inverter is capable of producing thirteen levels of output-voltage levels from the dc supply voltage. The proposed inverter system is capable of producing thirteen level of output voltage levels dc supply voltage by using three full bridge cascaded topology type inverter. In this project has used to three H-bridge inverter with different dc sources. The multi-level inverters promising the high performance with reduced EMI and harmonics. The proposed project is thirteen-level inverter was designed and results were also shown in the thesis.This project is focused on minimizing the number of semiconductors devices for a given number of levels. Index Terms: Inverter, electrical drives, cascaded, high power, multilevel inverter, reliability.

Single-Phase Seven-Level Grid-Connected Inverter for Photovoltaic System

This paper proposes a single-phase seven-level inverter for grid-connected photovoltaic systems, with a novel pulsewidth-modulated (PWM) control scheme. Three reference signals that are identical to each other with an offset that is equivalent to the amplitude of the triangular carrier signal were used to generate the PWM signals. The inverter is capable of producing seven levels of output-voltage levels (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> , 2V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> /3, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> /3, 0, -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> , -2V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> /3, -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> /3) from the dc supply voltage. A digital proportional-integral current-control algorithm was implemented in a TMS320F2812 DSP to keep the current injected into the grid sinusoidal. The proposed system was verified through simulation and implemented in a prototype.