Single-path Delay Feedback Architecture Research Articles

Design and Implementation of N-Point FFT Processor for MIMO-OFDM Systems using Radix N

This paper presents Single-path Delay Feedback (SDF) architecture for implementing Fast Fourier Transform (FFT) for Multiple-Input Multiple-Output Orthogonal Frequency Division Frequency Multiplexing (MIMO-OFDM). The architecture of Single-path Delay Feedback and memory scheduling are the basic concepts used to implement the FFT processor with variable length. Depending on the SDF architecture, we implement the FFT processor-based design which is proposed in this paper. In this paper, we use MIMOOFDM high data rates, high efficiency and high throughput. In this paper, we use radix-4 algorithm to implement the sequence because the speed of the operation is high. The functionality verification and the synthesis are carried out by using XLINIX.14.2.

VLSI Implementation of Reconfigurable FFT Processor Using Vedic Mathematics

Fast Fourier transform has been used in wide range of applications such as digital signal processing and wireless communications. In this we present a implementation of reconfigurable FFT processor using single path delay feedback architecture. To eliminate the use of read only memory’s (ROM’S). These are used to store the twiddle factors. To achieve the ROM-less FFT processor the proposed architecture applies the bit parallel multipliers and reconfigurable complex multipliers, thus consuming less power. The proposed architecture, Reconfigurable FFT processor based on Vedic mathematics is designed, simulated and implemented using VIRTEX-5 FPGA. Urdhva Triyakbhyam algorithm is an ancient Vedic mathematic sutra, which is used to achieve the high performance. This reconfigurable DIF-FFT is having the high speed and small area as compared with other conventional DIF-FFT

Area Efficient Fft/Ifft Processor for Wireless Communication

Fast Fourier Transform (FFT) processing is one of the key procedures in popular Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Structured pipeline architectures, low power consumption, high speed and reduced chip area are the main concerns in this VLSI implementation. In this paper, the efficient implementation of FFT/IFFT processor for OFDM applications is presented. The processor can be used in various OFDM-based communication systems, such as worldwide interoperability for Microwave access (Wi-Max), Digital Audio Broadcasting (DAB), Digital Video Broadcasting-Terrestrial (DVBT). We adopt single-path delay feedback architecture. To eliminate the Read Only Memories (ROM’s) used to store the twiddle factors, this proposed architecture applies a reconfigurable complex multiplier to achieve a ROM-less FFT/IFFT processor and to reduce the truncation error we adopt the fixed width modified booth multiplier. The three Processing Elements (PE’s), Delay-Line (DL) buffers are used for computing IFFT. Thus we consume the low power, lower hardware cost, and high efficiency and reduced chip size.

Low-power variable-length fast Fourier transform processor

Fast Fourier transform (FFT) processing is one of the key procedures in the popular orthogonal frequency division multiplexing (OFDM) communication systems. Structured pipeline architectures and low power consumption are the main concerns for its VLSI implementation. In the paper, the authors report a variable-length FFT processor design that is based on a radix-2/4/8 algorithm and a single-path delay feedback architecture. The processor can be used in various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T), asymmetric digital subscriber loop (ADSL) and very-high-speed digital subscriber loop (VDSL). To reduce power consumption and chip area, special current-mode SRAMs are adopted to replace shift registers in the delay lines. In addition, techniques including complex multipliers containing three real multiplications, and reduced sine/cosine tables are adopted. The chip is fabricated using a 0.35 /spl mu/m CMOS process and it measures 3900 /spl mu/m /spl times/ 5500 /spl mu/m. According to the measured results, the 2048-point FFT operation can function correctly up to 45 MHz with a 3.3 V supply voltage and power consumption of 640 mW. In low-power operation, when the supply voltage is scaled down to 2.3 V, the processor consumes 176 mW when it runs at 17.8 MHz.