Single Opamp Research Articles

A Dual-Mode Continuous–Time Sigma-Delta Modulator With a Reconfigurable Loop Filter Based on a Single Op-Amp Resonator

A Dual-Mode Continuous–Time Sigma-Delta Modulator With a Reconfigurable Loop Filter Based on a Single Op-Amp Resonator

A Single Op-Amp Resonator-Based Continuous-Time Sigma–Delta Modulator With Time-Division Switching for Excess Loop Delay Compensation

A Single Op-Amp Resonator-Based Continuous-Time Sigma–Delta Modulator With Time-Division Switching for Excess Loop Delay Compensation

Analysis and Comparison of Two Stage and Single Stage Operational Amplifiers Using 0.18µm Technology

Operational amplifier exists in many numbers of configurations. The there are many types of the Operational amplifiers. These are: two stage, single stage, three stage and multistage amplifiers. Identifying the better op amp is important to get better application. The better op amp will be selected by considering the performance parameters (DC Gain, Slew Rate, Power Dissipation, etc.) of op amp. In project work a two stage cmos and single stage CMOS operational has been compared and contrasted based on values of their performance parameters by using 0.18µm CMOS technology and the same power supply (5V). Based on these values, By comparing the performance parameters single stage CMOS op amp is more stable and operate longer duration of time than two stage cmos op amp with small energy loss; while two stage op amp produces the output which is twice larger than single stage op amp, and also the noise in the output of two stage op amp is less than single stage op amp. So to get more output it is better to use two stage op amps. By results and reasons suitable choices for high gain and high performance applications are two stage topologies.

Design and Simulation of Op-Amp Based Neuron Circuit

Abstract: Combining CMOS analog spike neurons with memory synapses, neuromorphic chips can provide massively parallel processing and density of neural networks, providing a promising solution for brain inspired computing. This work demonstrates a leaky integral firing neuron design that implements current integral and synaptic driven dualmode operation, and crossbar resistance synaptic enabled in situ learning with a single op amp. The proposed design was implemented with 0.18 μm CMOS technology.

Development of Educational Kit for Practical Course in the Topic of Phase-Shift RC Oscillator

This research develops a phase-shift RC Oscillator trainer kit that can be used to give undergraduate students an understanding of one of the materials related to analog circuit practicum. The Oscillator is one of the essential subtopics to be examined thoroughly by electrical engineering students. Furthermore, the Resistor and Capacitor modules were provided separately to be connected to the trainer through jumper cables. The phase-shift RC circuit in the trainer kit used a single Op-Amp 741 while the Network model utilized an Inverting Amplifier to determine the gain which must be ≥ 29 times, therefore, Rfeedback ≥ 29 Rgain (Rfeedback = 30 kΩ and Rgain = 1 kΩ). Two tasks in this learning media were completed by students, namely measuring the output frequency and observing the phase shift. The output signal on this trainer kit was observed using only an Oscilloscope and a frequency counter. The phase inverter of the phase-shift RC Oscillator adjusts the output signal by 180o and sends feedback to the input, therefore, there is positive feedback. Meanwhile, the trainer kit had an output frequency specification of ~649 Hz (C = 100 nF, R = 1 kΩ) and it shifts the phase by 60o on each RC network. Using 2 and 3 R-C networks, the phase shifts were 120o and 180o, respectively. The trainer kit was packaged in a box made of acrylic with dimensions l x w x h = 20 cm x 28 cm x 5 mm. Through a questionnaire consisting of 13 criteria, this trainer kit was declared valid, namely r count > 0.2960 (5%) and reliable (Cronbach's alpha > 0.60, which was 0.732) to be used as a learning media based on user responses, namely students (N = 35). In the context of technical education, this trainer kit also supports the efficient implementation of practicum without compromising the learning objectives due to the ease of operation (plug & play through jumper cables) compared to fully assembling the circuit using a project board.

Low-noise amplification of voltage response for thermopile optical detectors

A technique is presented to amplify the voltage response of thermopile optical detectors. It is based on the parallel combination of multiple operational amplifiers. The background noise of the voltage response has been deceased, which significantly improves the repeatability of the measurement results. Thus, this technique enables the same detector to measure weaker optical power or irradiance at the same precision level. The corresponding amplifying circuit is designed and fabricated. For the same detector, the experimental results show that the standard deviation of the background noise of the combined n op-amps is about lower comparing with the conventional single op-amp scheme, which is consistent with the theoretical expectations. Furthermore, the lasers of 10 μW and 1μW were also measured by the specific detector and the amplifier circuit. For a 10 μW response, the measurement repeatability of the 8-combined op-amps is about 1.4%, which is better than the 3.3% of a single op-amp. For 1 μW laser, the measurement result of voltage response of the 8-combined op-amps can be precisely quantified; however, the result of the single op-amp is hardly distinguished. The presented technique based on multiple op-amps is practical and can be potential in many applications. We hope this technique could offer help for expanding the measurement ranges of thermopile optical detectors at weaker optical power and irradiance.

A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp

This paper proposes a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order continuous-time delta-sigma modulator (CTDSM) with a single amplifier biquad (SAB) and excess loop delay (ELD) merged integrator. The integrator enables a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order noise-shaping together with ELD compensation with just a single Opamp and feedback DAC. A three-stage Opamp with a hybrid frequency-compensation scheme is presented, which achieves high gain and large unity-gain bandwidth (UGBW) with low power. The circuit secures an extra order noise-shaping through a passive noise-shaping SAR (NS-SAR) quantizer (QTZ) while further incorporating a preliminary sampling and quantization (PSQ) technique, the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> order NS QTZ can run at 1.5 GHz with 6b. The design, implemented in 28 nm, obtains 74.4 dB SNDR with 50 MHz bandwidth while consuming 10.4 mW from 1.5 V and 1 V power supplies. The prototype attains a dynamic range of 80.6 dB with a Schreier FOM of 171.2 dB. With the presented integrator and Opamp, the loop filter only consumes 14 % of the total DSM power consumption.

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR

A novel active noise-shaping SAR ADC with on- chip digital DAC calibration is presented. To relax the design of the single op-amp used as an integrator, correlated double sampling (CDS) and correlated level shifting (CLS) were implemented. CDS minimizes the offset of the integrator and reduces the flicker noise, while CLS boosts the gain of the op-amp and reduces the power consumption. Also, a two-step incremental ADC based digital DAC calibration scheme was implemented to cancel the DAC mismatch errors and parasitics effects. The ADC was fabricated in 0.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. It achieved 85.1 dB DR, 82.6 dB SNDR and 90.9 dB SFDR within a 2 kHz signal bandwidth with an oversampling ratio OSR = 32. It consumes 40.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power using a 1.6 V power supply.

67 dB SNDR 20 kHz BW SC third‐order modulator with single Op‐Amp and 20 µW power consumption for bio‐medical applications

This paper presents a single loop 3rd order discrete-time Sigma–Delta Modulator ( Σ Δ M ) using a single operational amplifier (Op-Amp). The proposed Σ Δ M utilises delay-based discrete-time integrators and a single Op-Amp is used to implement all the integrators of the proposed design. The delay-based design helps in relaxing the settling time requirement of an integrator, also the error due to slewing in the output of the integrator is avoided. A switched capacitor Op-Amp based proposed design is simulated in standard 180~nm CMOS technology with a resolution of 10.75 bits. The proposed Σ Δ M achieves a signal-to-noise-distortion ratio (SNDR) of 66.48 dB and dynamic range (DR) of 70 dB. An input signal of −4 dBFS magnitude at a frequency of 2.125 kHz is sampled with a sampling frequency of 1.024 MHz. The proposed circuit is designed for a bandwidth (BW) of 20 kHz with an over-sampling-ratio (OSR) of 25.6. The proposed modulator achieves a figure-of-merit (FOMS/FOMW) of 156.48 dB/0.290 (pJ/conversion-step) with the total power consumption of 20 µW at 1.8 V supply voltage (VDD). A Monte-Carlo simulation for the SNDR of the proposed design is done and the achieved mean and standard deviation (SD) is 66.09 dB and 1.025 respectively for 1000 samples.

A new chaotic oscillator containing generalised memristor, single op-amp and RLC with chaos suppression and an application for the random number generation

In this paper, a new chaotic oscillator consists of a single op-amp, two capacitors, one resistor, one inductor, and memristive diode bridge cascaded with an inductor is proposed. The proposed chaotic oscillator has a line of equilibria. In the new oscillator circuit, negative feedback, i.e. inverting terminal of the op-amp is used, and the non-inverting terminal is grounded. The new oscillator has chaotic, periodic, quasi-periodic behaviours, as seen from the Lyapunov spectrum plots. Some more theoretical and numerical tools are used to present the dynamical behaviours of the new oscillator like bifurcation diagram, phase plot. Further, a non-singular terminal sliding mode control (N-TSMC) is designed for the suppression of the chaotic states of the new oscillator. An application of the new oscillator is shown by designing a chaos-based random number generator. Raspberry Pi 3 is used for the realisation of the random number generator.

Simple linearising front‐end‐circuit for giant magneto‐resistance sensors

A simple and efficient linearisation front-end circuit for giant magneto-resistance (GMR) sensors are presented. This circuit essentially uses only a single opamp to linearise the (non-linear) GMR sensor output. A novel methodology that places an active GMR element, present inside the GMR sensor, in the feedback loop of the opamp is employed for linearisation. Initial validation of the front-end is performed using simulation and emulation studies. Then, the front-end, fabricated on a printed-circuit board, is interfaced with a GMR sensor. Experimentation showed output non-linearity is around 0.6%. The proposed front-end possess merits, like, low component-count and minimal error, no requirement of expensive amplifiers or matched resistors for linearisation, fast response, over the existing methods.

EM-Comm

Touch-based communication offers a direct and intuitive way for users to initiate and control data transfer when using tangible and ubiquitous interfaces. However, this requires that each interactive device be instrumented with a dedicated radio transmitter, which limits many applications. While not all devices have radio hardware, all devices do emit small amounts of electromagnetic noise in the form of EMI. We argue that if properly modulated these electromagnetic emissions can be used as an untapped communication channel capable of transmitting arbitrary data. To enable this, a spread spectrum frequency shift keying modulation scheme has been developed to encode data onto the device’s EMI. When the device is touched by a user, the data encoded EMI signal travels through their body and into our custom wrist band, consisting of a single op-amp and MCU. Our results show that we are able to turn electronic primitives such as LEDs, buttons, I/O lines, LCD screens, motors and power supplies into radio transmitters capable of touch communication. Effective data rates range from 5.8Kbps to 22 bit per image depending on the primitive used. To demonstrate this new communication technique, we develop several interactive experiences where users can retrieve complex information such as the function of buttons on a device, directions embedded into a LCD screen, and simplified device pairing. Ultimately, EM-Comm enables nearly any electronic device to be turned into a touch-based radio transmitter with only a software upgrade.

A Self-Biased Active Voltage Doubler for Energy Harvesting Systems

An active voltage doubler utilizing a single supply op-amp for energy harvesting system is presented. The proposed doubler is used for rectification process to achieve both acceptably high power conversion efficiency (PCE) and large rectified DC voltage. The incorporated op-amp is self-biased, meaning no external supply is needed but rather it uses part of the harvested energy for its biasing. The proposed active doubler achieves maximum power conversion efficiency (PCE) of 61.7% for a 200 Hz sinusoidal input of 0.8 V for a 20 KΩ load resistor. This efficiency is 2 times more when compared with the passive voltage doubler. The rectified DC voltage is almost 2 times more than conventional passive doubler. The relation between PCE and the load resistor is also presented. The proposed active voltage doubler is designed and simulated in LF 0.15 μm CMOS process technology using Cadence virtuoso tool.

Chaos in a Single Op-Amp–Based Jerk Circuit: Experiments and Simulations

We report a five-component autonomous chaotic oscillator of jerky type, hitherto the simplest of its kind, using only one operational amplifier. The key component of the circuit is a junction field-effect transistor operating in its triode region, which provides a nonlinear resistor of antisymmetrical current-voltage characteristic, emulating a Colpitts-like chaotic circuit. We describe the experimental results illustrating the dynamical behavior of the circuit. In addition, we report numerical simulations of a model of the circuit which display good agreement with our measurements.

A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and &lt;italic&gt;In Situ&lt;/italic&gt; Learning

Nanoscale resistive memories are expected to fuel dense integration of electronic synapses for large-scale neuromorphic system. To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in-situ learning and computing while driving a large number of resistive synapses is desired. This work presents a novel leaky integrate-and-fire neuron design which implements the dual-mode operation of current integration and synaptic drive, with a single opamp and enables in-situ learning with crossbar resistive synapses. The proposed design was implemented in a 0.18 $\mu$m CMOS technology. Measurements show neuron's ability to drive a thousand resistive synapses, and demonstrate an in-situ associative learning. The neuron circuit occupies a small area of 0.01 mm$^2$ and has an energy-efficiency of 9.3 pJ$/$spike$/$synapse.

Design and development of a low-cost biphasic charge-balanced functional electric stimulator and its clinical validation.

Functional electric stimulators that produce near-ideal, charge-balanced biphasic stimulation waveforms with interphase delay are considered safer and more efficacious than conventional stimulators. An indigenously designed, low-cost, portable FES device named InStim is developed. It features a charge-balanced biphasic single channel. The authors present the complete design, mathematical analysis of the circuit and the clinical evaluation of the device. The developed circuit was tested on stroke patients affected by foot drop problems. It was tested both under laboratory conditions and in clinical settings. The key building blocks of this circuit are low dropout regulators, a DC-DC voltage booster and a single high-power current source OP-Amp with current-limiting capabilities. This allows the device to deliver high-voltage, constant current, biphasic pulses without the use of a bulky step-up transformer. The advantages of the proposed design over the currently existing devices include improved safety features (zero DC current, current-limiting mechanism and safe pulses), waveform morphology that causes less muscle fatigue, cost-effectiveness and compact power-efficient circuit design with minimal components. The device is also capable of producing appropriate ankle dorsiflexion in patients having foot drop problems of various Medical Research Council scale grades.

Disturbance Observer-Based Voltage Regulation of Current-Mode-Boost-Converter-Interfaced Photovoltaic Generator

In this paper, a robust control method based on a disturbance observer is proposed to regulate the terminal voltage of a photovoltaic generator, interfaced by a current mode-controlled boost dc-dc converter. The combined generator-converter-load system possesses a nonlinear behavior, highly dependent on operation point and environmental variables, thus burdening the control task. It is shown that employing a typical linear controller, designed according to a single nominal operating point, results in a closed-loop performance, varying from a highly overdamped near open-circuit condition to greatly underdamped around short-circuit conditions. On the other hand, when the proposed robust controller is utilized, the closed-loop performance remains nearly nominal throughout the whole operation range. In addition, it is shown that, by sacrificing the performance in the vicinity of the open-circuit point, it is possible to implement the controller using a single op-amp with a reduced part count. Simulation and experimental results are presented to verify the proposed method.

Novel Single-CFOA-based Sinusoidal Oscillator Capable of Absorbing All Parasitic Impedances

Although a large number of single current feedback op-amp (CFOA)-based sinusoidal oscillator circuits have been proposed in the literature, to the best knowledge of the authors, no single-CFOA oscillator configuration has been reported earlier which can absorb all the parasitic impedances of the CFOA in the various external passive elements employed. The major intention of this paper is to report such a circuit. The workability of the proposed circuit has been confirmed by experimental results employing an AD844-type CFOA.

Intelligent GA optimizer for single supply operational amplifier and MMIC low noise amplifier

Single-Supply Operational Amplifier (Op-Amp) is important to the applications on battery-powered equipments whereas MMIC Low Noise Amplifier (LNA) is a type of integrated circuit device used in capturing operating signal in microwave frequency. This paper presents an optimization study of a Single-Supply Op-Amp and a MMIC LNA using Genetic Algorithm (GA). GA is proposed to optimize multiple input variables so as to achieve the required circuit design outputs. In Single-Supply Op-Amp, a single objective GA optimization study is conducted. Based on the single objective circuit design justification, GA is further investigated for its capability to deal with multiple design objectives in 5 GHz MMIC LNA. In this research, the Single-Supply Op-Amp design is synthesized via LTSpice whereas the MMIC LNA design is simulated through Agilent Advanced Design System (ADS). The optimization performance of GA for both single and multi-objective circuit designs is studied and the developed multi-objective GA optimizer is further compared with ADS built-in optimizers of Gradient and Quasi-Newton respectively. From the results, GA is shown to be capable in optimizing both single objective Op-Amp and multi-objective LNA.

A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder

A third-order low-distortion delta-sigma modulator (DSM), whose third-order noise-shaping ability is achieved by just a single opamp, is proposed. Since only one amplifier is required in the whole circuit, the designed DSM is very power efficient. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the digital-to-analog converter (DAC) array of a successive-approximation-type quantizer, is used. In addition, the feedback path timing is extended from a nonoverlapping interval for the conventional low-distortion structure to half of the clock period, so that the strict operation timing issue with regard to quantization and the dynamic element matching (DEM) logic operation can be solved. In the proposed DSM structure, the features of the unity-gain signal transfer function (STF) and finite-impulse-response (FIR) noise transfer function (NTF) are still preserved, and thus advantages such as a relaxed opamp slew rate and reduced output swing are also maintained, as with the conventional low-distortion DSM. Moreover, the memory effect in the proposed DSM is analyzed when employing the opamp sharing for integrators. The proposed third-order DSM with a 4-bit SAR ADC as the quantizer is implemented in a 90-nm CMOS process. The post-layout simulations show a 79.8-dB signal-to-noise and distortion ratio (SNDR) in the 1.875-MHz signal bandwidth (OSR=16). The active area of the circuit is 0.35 mm2 and total power consumption is 2.85 mW, resulting in a figure of merit (FOM) of 95 fJ/conversion-step. key words: delta-sigma modulator, DSM, opamp sharing, relaxed dynamic element matching (DEM) timing