Single Miller Capacitor Research Articles

A three-stage single-miller CMOS OTA with no lower load capacitor limit

This work proposes a Single Miller Capacitor (SMC) compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors with a zero minimum load capacitor. The proposed three-stage OTA does not require a minimum load capacitor for OTA to be stable. The proposed work uses two different feed-forward transconductors to enhance the small-signal and large-signal performances of the OTA. This OTA achieves more than 70° phase margin and more than 10dB gain margin with a load capacitor range of 0 to 500pF and consumes less quiescent current. The proposed OTA uses a smaller SMC of 2pF to drive a wide range of load capacitors. Furthermore, it saves the active area of the chip. The proposed OTA is simulated in a cadence virtuoso tool using UMC 90nm CMOS technology with BSIM4 MOSFETs.

Single Miller frequency compensation: Three stage CMOS

A simple and efficient frequency compensation network is exploited for a three-stage amplifier. Single Miller capacitor at the output of a differential stage forms compensation network. This configuration benefits from less dependency to compensation capacitor since only one and small value capacitor is used. This stems from the fact that the differential block intensifies Miller effect virtually by multiplying its gain value to capacitor value. The structure is modeled symbolically with exclusive formulation for involved dynamics. Also, circuit implementation is performed via 0.18μm CMOS technology. Both theoretical and simulation results are compatible with negligible error. According to the simulation results, proposed three stage amplifiers in this work show 135 dB, 7.5 MHz and 85º as DC gain, GBW and PM respectively.

Miller compensated four-stage OTA with Q-reduction for wide range of load capacitors

This paper proposes a four-stage miller compensated Operational Transconductance Amplifier (OTA) with Q-reduction. The multi-stage OTA is an ideal choice for the submicron CMOS technology. The main challenge in multi-stage OTA design with low quiescent current is the increased number of high impedance nodes. These high impedance nodes create stability issues. Usually, the multi-stage OTA requires the compensation capacitor in the order of pF which consumes more chip area; moreover, it reduces the bandwidth of the OTA. The proposed four-stage OTA uses a single miller capacitor Cm along with a feed-forward capacitor Cf. The four-stage OTA uses only 500fF of total compensation capacitors to stabilize a complex four-stage OTA. The proposed OTA uses multiple feed-forward paths to enhance the small-signal and the large-signal performances of the OTA. The four-stage OTA achieves a better transient response with the settling time of 510ns under low quiescent power of 63.6μW for the wide range of load capacitors of 5pF to 100pF.

Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review

AbstractThis paper presents a systematic analytical comparison of the single‐Miller capacitor frequency compensation techniques suitable for three‐stage complementary metal–oxide–semiconductor (CMOS) operational transconductance amplifiers (OTAs). The comparison is carried out with the aid of a figure of merit that expresses a trade‐off among gain‐bandwidth product, load capacitance, and total transconductance, for equal values of the phase margin. The results found can be used before the transistor‐level design step and provide useful guidelines for the optimization of the small‐signal performance. Simulations by using a 65‐nm standard CMOS technology confirming the effectiveness of the theoretical comparison for 10 different OTA topologies are also provided.

High-Performance Multi-Stage CMOS OTA Design Using Differential Block as Compensation Network

This work presents an effective and straightforward frequency compensation scheme in CMOS three-stage amplifiers. Using a differential block in the compensation network, the proposed circuit shows independent and large first dominant pole regarding the DC gain path. The presented three-stage architecture is frequency-compensated just by a single Miller capacitor. Mathematical analysis is presented along with ample simulations that are performed using TSMC 0.18-[Formula: see text]m CMOS technology. According to the results, the proposed circuit shows DC gain equal to 118[Formula: see text]dB, GBW equal to 466[Formula: see text]MHz, PM equal to 74.3∘ and 1.2[Formula: see text]mW as power consumption, respectively. The high values of DC gain and GBW make the proposed amplifier appropriate for more speedy operations such as high-speed modulators and data converters.

A high‐performance CMOS four‐stage amplifier

AbstractIn this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.

High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of <inline-formula> <tex-math notation="LaTeX">${C}_{L}$ </tex-math> </inline-formula>

This brief presents a low-power, area-efficient three-stage CMOS operational transconductance amplifier (OTA) suitable for very large capacitive loads, C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> . A single Miller capacitor and an inverting current buffer embedded in the input stage are exploited to implement the frequency compensation network. An additional feed-forward path and a slew rate enhancer are also utilized to improve the large-signal transient response. Detailed small-signal analysis reveals that the proposed OTA does not exhibit an upper limit of drivable C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> . The OTA is fabricated in a standard 0.35-μm technology and occupies 0.0027 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area. Under 1.4-V supply and 6.36-μA quiescent current consumption, it provides a dc gain greater than 110 dB and is stable for any C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> larger than 5 nF. Comparison with the state of the art shows remarkable improvement of both small- and large-signal performance.

Three stages CMOS operational amplifier frequency compensation using single Miller capacitor and differential feedback path

This study describes a new and simple frequency compensation for three stages amplifiers based on revered nested Miller compensation (RNMC) structure. Using only one and small compensation capacitor reduced circuit complexity and die area while shows better performance compared to RNMC. Also the proposed method is unconditional stable due to cancellation of second dominant pole by a zero. Ample simulations are performed using HSPICE and TSMC 0.18 µm CMOS technology to verify robustness of presented circuit. Simulation results show 114 dB, 6.66 MHz and 360 µW as DC gain, GBW and power consumption respectively.

Low-voltage high-gain large-capacitive-load amplifiers in 90-nm CMOS technology

Low-voltage and low-power multistage operational transconductance amplifiers with new and efficient gain boosting and frequency compensation schemes are proposed in this paper. The presented amplifiers are designed to drive large capacitive loads with small power consumption at low-voltage supplies. The compensation schemes exploit a single Miller capacitor and an active feedback to form the main negative feedback loops for pole splitting and two feedforward paths. The new gain boosting technique discussed here improves the dc gain with negligible effect on the frequency response. The analysis and design procedures are discussed and the performance enhancements of the amplifiers are verified. The proposed OTAs have been implemented in a standard 90-nm CMOS process and the post-layout simulation results are reported. The amplifiers consume 8.7μW and 8.1μW at 0.5-V supplies and achieve 12.65MHz and 2MHz gain-bandwidth products while driving 150-pF and 15-nF capacitive loads, respectively.

A new frequency compensation technique for three stages OTA by differential feedback path

AbstractA new single Miller capacitor for frequency compensation of three‐stage amplifier is proposed in this paper. In this scheme, a differential stage in which its negative and positive inputs are connected to the output and input nodes of third stage with a cascade capacitor forms the compensation block of a conventional three‐stage amplifier. Analysis shows that this configuration significantly improves the frequency domain performances of total circuit such as phase margin (PM) and gain‐bandwidth product (GBW) with just a very small amount of compensation capacitor. A three‐stage amplifier has been simulated with and without a differential feedback path in a 0.18 µm complementary metal–oxide–semiconductor (CMOS). The simulated amplifier with a 100 pF capacitive load achieved more than 9 MHz GBW and 83° PM while the compensation is less than 0.2% of load capacitor. An amplifier based on conventional nested Miller compensation can just achieve less than 0.23 MHz GBW with the same load, while using more than 100 pF as compensation capacitor. So this method shows an improvement of a factor of 40 in GBW and reduction of a factor of 550 in the size of compensation capacitor. It is a suitable strategy for ON‐CHIP compensation in comparison to other methods. Copyright © 2014 John Wiley &amp; Sons, Ltd.

Design of a Three-Stage Amplifier with Single Miller Capacitor Feedforward Compensation

An efficient three-stage amplifier with a new compensation method called single Miller capacitor feedforward compensation (SMFFC) which is suitable for large capacitive load applications are introduced in this paper. The overall layout area of the amplifier can be significantly reduced without influencing their stability by using a single Miller compensation capacitor in a three-stage amplifier. Pole-splitting and feedforward techniques are effectively combined in this compensation method to achieve a better performance.

ACTIVE-FEEDBACK SINGLE MILLER CAPACITOR FREQUENCY COMPENSATION TECHNIQUES FOR THREE-STAGE AMPLIFIERS

This paper presents two novel active-feedback single Miller capacitor frequency compensation techniques for low-power three-stage amplifiers. These techniques include the active-feedback single Miller capacitor frequency compensation (AFSMC) and the dual active-feedback single Miller capacitor frequency compensation (DAFSMC). In the proposed techniques, only one Miller capacitor in series with a current buffer is utilized. The main advantages of the proposed three-stage amplifiers are the enhanced unity-gain bandwidth and the reduced silicon area. Small-signal analyses are performed and the design equations are obtained. Extensive HSPICE simulation results are provided to show the usefulness of the proposed AFSMC and DAFSMC amplifiers in both large and small capacitive loads.

A 6-$\mu$W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 μW under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 μs.

A controllable resistor and its applications in pole-zero tracking frequency compensation methods for LDOs

This paper presents a controllable resistor, which is formed by a MOS-resistor working in the deep triangle region and an auxiliary circuit. The auxiliary circuit can generate the gate-source voltage which is proportional to the output current of an low dropout regulator for the MOS-resistor. Thus, the equivalent output resistance of the MOS-resistor is inversely proportional to the output current, which is a suitable feature for pole-zero tracking frequency compensation methods. By switching the type of the MOS-resistor and current direction through the auxiliary circuit, the controllable resistor can be suitable for different applications. Three pole-zero tracking frequency compensation methods based on a single Miller capacitor with nulling resistor, unit-gain compensation cell and pseudo-ESR (equivalent serial resistor of load capacitor) power stage have been realized by this controllable resistor. Their advantages and limitations are discussed and verified by simulation results.

Single Miller capacitor frequency compensation with nulling resistor for three‐stage amplifiers

AbstractA frequency compensation technique for three‐stage amplifiers is introduced. The proposed solution exploits only one Miller capacitor and a resistor in the compensation network. The straightness of the technique is used to design, using a standard CMOS 0.35‐µm process, a 1.5‐V OTA driving a 150‐pF load capacitor. The dc consumption is about 14µA at DC and a 1.8‐MHz gain–bandwidth product is obtained, providing significant improvement in both (MHzpF)/mA and ((V/µs)pF)/mA performance parameters. Copyright © 2007 John Wiley &amp; Sons, Ltd.

CMOS low dropout linear regulator with single Miller capacitor

A 2–5V 150 mA CMOS low dropout (LDO) linear regulator with a single Miller capacitor of 4pF is presented. The proposed LDO regulator with a bandgap voltage reference has been fabricated in a 0.35 µm CMOS process and the active chip area is 485×586 µm. The maximum output current is 150 mA and the regulated output voltage is 1.8 V.

Single Miller capacitor frequency compensation technique for low-power multistage amplifiers

Due to the rising demand for low-power portable battery-operated electronic devices, there is an increasing need for low-voltage low-power low-drop-out (LDO) regulators. This provides motivation for research on high-gain wide-bandwidth amplifiers driving large capacitive loads. These amplifiers serve as error amplifiers in low-voltage LDO regulators. Two low-power efficient three-stage amplifier topologies suitable for large capacitive load applications are introduced here: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). Using a single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Pole-splitting and feedforward techniques are effectively combined to achieve better small-signal and large-signal performances. The 0.5-/spl mu/m CMOS amplifiers, SMC, and SMFFC driving a 25-k/spl Omega///120-pF load achieve 4.6-MHz and 9-MHz gain-bandwidth product, respectively, each dissipates less than 0.42 mW of power with a /spl plusmn/1-V power supply, and each occupies less than 0.02 mm/sup 2/ of silicon area.