Single Memory Location Research Articles

Decoupling lock-free data structures from memory reclamation for static analysis

Verification of concurrent data structures is one of the most challenging tasks in software verification. The topic has received considerable attention over the course of the last decade. Nevertheless, human-driven techniques remain cumbersome and notoriously difficult while automated approaches suffer from limited applicability. The main obstacle for automation is the complexity of concurrent data structures. This is particularly true in the absence of garbage collection. The intricacy of lock-free memory management paired with the complexity of concurrent data structures makes automated verification prohibitive. In this work we present a method for verifying concurrent data structures and their memory management separately. We suggest two simpler verification tasks that imply the correctness of the data structure. The first task establishes an over-approximation of the reclamation behavior of the memory management. The second task exploits this over-approximation to verify the data structure without the need to consider the implementation of the memory management itself. To make the resulting verification tasks tractable for automated techniques, we establish a second result. We show that a verification tool needs to consider only executions where a single memory location is reused. We implemented our approach and were able to verify linearizability of Michael&Scott's queue and the DGLM queue for both hazard pointers and epoch-based reclamation. To the best of our knowledge, we are the first to verify such implementations fully automatically.

Detection of High-Level Synchronization Anomalies in Parallel Programs

In parallel programs concurrency bugs are often caused by unsynchronized accesses to shared memory locations, which are called data races. In order to support programmers in writing correct parallel programs, it is therefore highly desired to have tools on hand that automatically detect such data races. Today, most of these tools only consider unsynchronized read and write operations on a single memory location. Concurrency bugs that involve multiple accesses on a set of correlated variables may be completely missed. Tools may overwhelm programmers with data races on various memory locations, without noticing that the locations are correlated. In this paper, we propose a novel approach to data race detection that automatically infers sets of correlated variables and logical operations by analyzing data and control dependencies. We develop an algorithm that is inspired by lockset analysis and combine it with happens-before analysis to provide the first hybrid, dynamic race detector for correlated variables. We implemented our approach on top of the Valgrind, a framework for dynamic binary instrumentation. Our evaluation confirmed that we can catch data races missed by existing detectors and provide additional information for effective bug fixing.

Improved loop tiling based on the removal of spurious false dependences

To preserve the validity of loop nest transformations and parallelization, data dependences need to be analyzed. Memory dependences come in two varieties: true dependences or false dependences. While true dependences must be satisfied in order to preserve the correct order of computations, false dependences are induced by the reuse of a single memory location to store multiple values. False dependences reduce the degrees of freedom for loop transformations. In particular, loop tiling is severely limited in the presence of these dependences. While array expansion removes all false dependences, the overhead on memory and the detrimental impact on register-level reuse can be catastrophic. We propose and evaluate a compilation technique to safely ignore a large number of false dependences in order to enable loop nest tiling in the polyhedral model. It is based on the precise characterization of interferences between live range intervals, and it does not incur any scalar or array expansion. Our algorithms have been implemented in the Pluto polyhedral compiler, and evaluated on the PolyBench suite.

New Memory Architecture for Rolling Shutter Wide Dynamic Range CMOS Imagers

In this work, the concept of reusing a memory location to significantly reduce the overall memory size for storing wide dynamic range (WDR) information in rolling shutter active pixel sensors (APSs) is discussed. At the high light level, WDR is achieved via multiple-resets and real time feedback, allowing a pixel to independently set its integration period as per its ambient light level. Traditionally these WDR bits are stored in a dedicated memory location for every pixel. We propose a new memory architecture which, in principal, is similar to time division multiplexing, such that it achieves memory size reduction by sharing a single memory location among a number of pixels as a function of time. The proposed architecture is ideally suited for rolling shutter APS, where each row is processed sequentially in time. Compared to a commonly used memory design, the proposed architecture becomes increasingly efficient as the pixel count increases, resulting in momentous savings in memory chip area and leakage power consumption. For a pixel array of 128 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\ast$</tex></formula> 128, only 14.2% of the commonly used memory bits are required, when using 7 WDR bits per pixel. This requirement reduces to 8.3% of the commonly used memory bits for a pixel array size of 4096 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\ast$</tex> </formula> 4096, rendering the purposed architecture particularly efficient for larger arrays. The savings in leakage power will track the corresponding savings in memory size and area especially for newer technologies. The purposed concept has been verified in design and simulation for a 128 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\ast$</tex></formula> 128 pixel array, fabricated in 180 nm technology.

A decision procedure for detecting atomicity violations for communicating processes with locks

The problem of interest is to verify data consistency of a concurrent Java program. In particular, we present a new decision procedure for verifying that a class of data races caused by inconsistent accesses on multiple fields of an object cannot occur (so-called atomic-set serializability). Atomic-set serializability generalizes the ordinary notion of a data race (i.e., inconsistent coordination of accesses on a single memory location) to a broader class of races that involve accesses on multiple memory locations. Previous work by some of the authors presented a technique to abstract a concurrent Java program into an EML program, a modeling language based on pushdown systems and a finite set of reentrant locks. Our previous work used only a semi-decision procedure, and hence provides a definite answer only some of the time. In this paper, we rectify this shortcoming by developing a decision procedure for verifying data consistency, i.e., atomic-set serializability, of an EML program. When coupled with the previous work, it provides a decision procedure for verifying data consistency of a concurrent Java program. We implemented the decision procedure, and applied it to detect both single-location and multi-location data races in models of concurrent Java programs. Compared with the prior method based on a semi-decision procedure, not only was the decision procedure 34 times faster overall, but the semi-decision procedure timed out on about 50% of the queries, whereas the decision procedure timed out on none of the queries.

A Survey of Multivalued Memories

Techniques of storing multiple bits of information in a single memory location are reviewed. Any of several states can be stored in ROM's by adjusting the threshold voltage or the size of a particular memory device. In dynamic RAM's, this can be achieved by varying the charge stored on the cell capacitor. The peripheral circuitry required to distinguish between the states stored in the memory areas is discussed.

Perfect Storage Representations for Families of Data Structures

In this paper we investigate the problem of finding efficient universal storage representations for certain families of data structures, such as the family $T_n$ of n-node binary trees, where the constituent parts of family members are labelled according to a uniform naming scheme. For example, each node of a tree in $T_n$ can be labelled by a binary string describing the sequence of left and right edges taken to reach that node from the root. If one preassigns a distinct memory location to each possible distinct name, then any member of $T_n$ can be stored by storing the contents of each node in the location assigned to the label of that node. However, this would require $2^n - 1$ memory locations and is wasteful of space, since certain labels can never occur together in a tree in $T_n $ and hence could share a single memory location. We consider the problem of minimizing the number of memory locations needed, viewed in the following general form:Consider a collection $\Gamma $ of labelled finite graphs,...