Single Instruction Multiple Data Architecture Research Articles

Parallel Implementation of K-Best Quadrature Amplitude Modulation Detection for Massive Multiple Input Multiple Output Systems

Massive MIMO (Multiple Input Multiple Output) systems impose significant processing burdens along with strict latency requirements. The combination of large-scale antenna arrays and wide bandwidth requirements for next-generation wireless systems creates an exponential increase in frontend to backend data. Balancing the processing latency and reliability is critical for baseband processing tasks such as QAM detection. While linear detection algorithms have low computational complexity, their use in Massive MIMO scenario has heavy degradation in error performance. Nonlinear detection methods such as Maximum Likelihood and Sphere Decoding have good error performance, but they suffer from high, variable, and uncontrollable computational complexity. For such cases, the K-best QAM detection algorithm can provide required control over the system performance while maintaining near-ML error performance. In this paper, hard-output, as well as soft-output K-best QAM detection, is implemented in a CPU by utilizing the multiple cores combined with vector processing. Similarly, hard-output detection in a GPU is implemented by leveraging the SIMD (Single Instruction, Multiple Data) architecture and Warp-based execution model. The processing time per bit and the energy consumption per bit are compared for CPU and GPU implementations for QAM constellation density and MIMO array size. The GPU implementation shows up to 5× processing latency per bit improvement and up to 120× energy consumption per bit improvement over the CPU implementation for typical QAM constellations such as 4, 16, and 64 QAM. GPU implementation also shows up to 125× improvement over CPU implementation in energy consumption per bit for larger MIMO configurations such as 24 × 24 and 32 × 32. Finally, the soft-output detector is combined with a LDPC (Low-Density Parity Check) decoder to obtain the FER (Frame Error Rate) performance for CPU implementation. The FER is then combined with frame processing latency to form a Goodput metric to demonstrate the latency and reliability tradeoff.

Serial and parallel kernelization of Multiple Hitting Set parameterized by the Dilworth number, implemented on the GPU

The NP-hard Multiple Hitting Set problem is the problem of finding a minimum-cardinality set intersecting each of the sets in a given input collection a given number of times. Generalizing a well-known data reduction algorithm due to Weihe, we show a problem kernel for Multiple Hitting Set parameterized by the Dilworth number, a graph parameter introduced by Foldes and Hammer in 1978 yet seemingly so far unexplored in the context of parameterized complexity theory. Using matrix multiplication, we speed up the algorithm to quadratic sequential time and logarithmic parallel time. We experimentally evaluate our algorithms. By implementing our algorithm on GPUs, we show the feasibility of realizing kernelization algorithms on SIMD (Single Instruction, Multiple Data) architectures.

Vectorizing and distributing number‐theoretic transform to count Goldbach partitions on Arm‐based supercomputers

SummaryIn this article, we explore the usage of scalable vector extension (SVE) to vectorize number‐theoretic transforms (NTTs). In particular, we show that 64‐bit modular arithmetic operations, including modular multiplication, can be efficiently implemented with SVE instructions. The vectorization of NTT loops and kernels involving 64‐bit modular operations was not possible in previous Arm‐based single instruction multiple data architectures since these architectures lacked crucial instructions to efficiently implement modular multiplication. We test and evaluate our SVE implementation on the A64FX processor in an HPE Apollo 80 system. Furthermore, we implement a distributed NTT for the computation of large‐scale exact integer convolutions. We evaluate this transform on HPE Apollo 70, Cray XC50, HPE Apollo 80, and HPE Cray EX systems, where we demonstrate good scalability to thousands of cores. Finally, we describe how these methods can be utilized to count the number of Goldbach partitions of all even numbers to large limits. We present some preliminary results concerning this problem, in particular a histogram of the number of Goldbach partitions of the even numbers up to 240.

Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Architectures with the CMS Detector

In the High–Luminosity Large Hadron Collider (HL–LHC), one of the most challenging computational problems is expected to be finding and fitting charged-particle tracks during event reconstruction. The methods currently in use at the LHC are based on the Kalman filter. Such methods have shown to be robust and to provide good physics performance, both in the trigger and offline. In order to improve computational performance, we explored Kalman-filter-based methods for track finding and fitting, adapted for many-core SIMD (single instruction, multiple data) and SIMT (single instruction, multiple thread) architectures. Our adapted Kalman-filter-based software has obtained significant parallel speedups using such processors, e.g., Intel Xeon Phi, Intel Xeon SP (Scalable Processors) and (to a limited degree) NVIDIA GPUs. Recently, an effort has started towards the integration of our software into the CMS software framework, in view of its exploitation for the Run III of the LHC. Prior reports have shown that our software allows in fact for some significant improvements over the existing framework in terms of computational performance with comparable physics performance, even when applied to realistic detector configurations and event complexity. Here, we demonstrate that in such conditions physics performance can be further improved with respect to our prior reports, while retaining the improvements in computational performance, by making use of the knowledge of the detector and its geometry.

Highly Parallel Vector Radix FFT for High Throughput Video Applications

The Vector Radix Fast Fourier Transform, with the inherent amenity for parallel implementation is very favourable for high throughput video processing applications. The conventional implementation of two-dimensional Fast Fourier Transform as one dimensional transforms of rows and columns can be replaced with this approach. This brief presents a novel Single Instruction Multiple Data architecture for the 8 × 8 vector radix Fast Fourier Transform implemented in Field-Programmable Gate Array with Digital Signal Processing Slice as the processing element. The performance metrics of the design is compared to the two dimensional Fast Fourier Transform implemented using one dimensional Fast Fourier Transform Intellectual Property from Xilinx. The analysis demonstrates the dominance of the design for high throughput low latency video applications.

A Work Efficient Parallel Algorithm for Exact Euclidean Distance Transform.

A fully-parallelized work-time optimal algorithm is presented for computing the exact Euclidean Distance Transform (EDT) of a 2D binary image with the size of n×n . Unlike existing PRAM (Parallel Random Access Machine) and other algorithms, this algorithm is suitable for implementation on modern SIMD (Single Instruction Multiple Data) architectures such as GPUs. As a fundamental operation of 2D EDT, 1D EDT is efficiently parallelized first. Specifically, the GPU algorithm for the 1D EDT, which uses CUDA (Compute Unified Device Architecture) binary functions, such as ballot(), ffs(), clz(), and shfl(), runs in O(log32n) time and performs O(n) work. Using the 1D EDT as a fundamental operation, the fully-parallelized work-time optimal 2D EDT algorithm is designed. This algorithm consists of three steps. Step 1 of the algorithm runs in O(log32n) time and performs O(N) ( N = n2 ) of total work on GPU. Step 2 performs O(N) of total work and has an expected time complexity of O(logn) on GPU. Step 3 runs in O(log32n) time and performs O(N) of total work on GPU. As far as we know, this algorithm is the first fully-parallelized and realized work-time optimal algorithm for GPUs. The experimental results show that this algorithm outperforms the prior state-of-the-art GPU algorithms.

CNFET-Based High Throughput SIMD Architecture

Carbon nanotube field effect transistor (CNFET), using the carbon nanotubes (CNTs) as the material for conducting, is a promising alternative of CMOS technology to overcome the “power wall” issue. Recently, a microprocessor solely based on CNFETs was fabricated and demonstrated, which is a big step forward to the industrial practice. However, CNFETs are inherently subject to much larger process variation or manufacturing defects; thereby it may cause significant design cost to build high performance processors. This is exacerbated in the large register file (RF) architectures widely used in single instruction multiple data (SIMD) architectures, e.g., general public utilities style processors, where the number of critical paths are multiplied by the SIMD width and thread count. In this paper, we seek cost-effective approaches to address the issues by judiciously exploiting the strong asymmetric spatial correlation in the variation unique to the CNFET fabrication process. This paper presents a microarchitectural model to characterize CNFET delay variation and malfunction, under which we show that the RF organizations coupled with the architectural schemes are critical to the performance and power consumption of the SIMD processor. Therefore, we propose several architectural techniques to mitigate the performance degradation and the impact of CNT metallization, leveraging the distinctive CNFET characteristics and the unique features in the SIMD processors. Experimental results verify the effectiveness of the proposed techniques and demonstrate the great opportunity offered by this new device technology.

Revised simplex algorithm for linear programming on GPUs with CUDA

The revised simplex algorithm (RSA) is a typical algorithm for solving linear programming problems. Many theoretical modifications have been done to make the algorithm more efficient, but almost all of them were based on single-instruction single-data architecture processors (CPUs), which could not make full use of the inherent parallel characteristics of RSAs. We propose a novel single-instruction multiple-data architecture processor (GPU) based on the RSA in this paper. The intensive matrix manipulations of a traditional RSA are offloaded to the GPU, which helps to make full use of its powerful parallel processing ability. We implemented the GPU-based RSA on compute unified device architecture (CUDA). Numerical experiments on randomly generated linear programs show that the GPU-based RSA can not only find the correct optimal solutions, but can also reach a speed of up to 100 times as fast as that of a CPU-based RSA: it also runs 3 to 11 times as fast as MATLAB.

Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures

This work presents a methodology for efficient exploration of data interleaving and data-to-memory mapping options for Single Instruction Multiple Data (SIMD) platform architectures. The system architecture consists of a reconfigurable clustered scratch-pad memory and a SIMD functional unit, which performs the same operation on multiple input data in parallel. The memory accesses contribute substantially to the overall energy consumption of an embedded system executing a data intensive task. The scope of this work is the reduction of the overall energy consumption by increasing the utilization of the functional units and decreasing the number of memory accesses. The presented methodology is tested using a number of benchmark applications with holes in their access scheme. Potential gains are calculated based on the energy models, both for the processing and the memory part of the system. The reduction in energy consumption after efficient interleaving and mapping of data is between 40% and 80% for the complete system and the studied benchmarks.

A Multi-functional Multi-precision 4D Dot Product Unit with SIMD Architecture

The floating-point (FP) four-dimensional vector inner product (4D dot product; DP4) is one of the most frequently performed operations in 3D graphics applications. Therefore, the hardware implementation of FP DP4 unit can be used in modern graphics processing units (GPUs) to speed up the performance. Unfortunately, the FP DP4 unit is power hungry and how to reduce its power consumption becomes very critical for the mobile GPUs. In this paper, a multi-functional multi-precision DP4 unit with single instruction multiple data (SIMD) architecture is proposed. Instead of additional discrete FP multipliers, adders, and multiply-add-fused units, the proposed architecture can perform not only one-way DP4 but also four-way multiplication, addition, and multiply-add-fused operations to decrease the hardware area. In addition, the proposed architecture can perform the above-mentioned FP operations with four precision modes (i.e., 23-, 18-, 13- and 7-bit modes) to reduce the power and energy consumptions when a little image distortion is allowable. The proposed design is fully pipelined with a latency of three cycles, a throughput of one cycle, and a cycle time of 2.8 ns in 90 nm CMOS technology. When compared with the one-precision DP4 unit, the proposed multi-precision DP4 unit can save about 7.2, 18.5, 32.2, and 49.6 % power consumption on average for 23-, 18-, 13- and 7-bit precision modes, respectively, at the expense of 3.7 % more area and 7.7 % longer delay.

An FPGA-Based SIMD Architecture for Video Compression with Scalable Throughput

Data processing using spatial parallelism from single instruction, multiple data (SIMD) machines can be used in image processing to improve system performance regarding data throughput. The spatial parallelism is an alternative for increasing the device operating frequency, generally limited by hardware constraints. In parallel architectures for video processing with high requirements in terms of data throughput, different processing units (PUs) simultaneously operate on pixels belonging to nonoverlapping regions of the image frame.

The SIMD accelerator for business analytics on the IBM z13

IBM z Systems™ have been hosting critical business applications across several industries including banking, healthcare, insurance, and retail for over 50 years. With the recent growth in the use of analytics in the business environment, more customers are seeking to integrate analytics into their core operational environments to enable real-time insight on operational data for competitive advantage. IBM z Systems support very high-performance computation for business analytics. The z System processors are typically higher frequency than any general-purpose microprocessor, and with the zEnterprise® 196 (z196) system, huge gains in performance were made through out-of-order execution. The robust cache hierarchy also provides additional performance boosts to high concurrency analytics operations. The IBM z13™ extends these performance improvements with a new SIMD (single-instruction, multiple-data) engine in the processor for targeted acceleration of business analytics workloads. This SIMD engine supports new instructions for three data types: integer, string, and floating-point. We provide an overview of the z13 SIMD architecture and show how it advances current architectures. We also discuss the compiler and math library support for this new architecture and provide a few examples of applications that can be accelerated by this new hardware feature on the z13.

Divergent Branch Threads Compaction for Efficient SIMD Control Flow

Wide Single instruction multiple data (SIMD) architectures are very important in the computeintensive applications. The SIMD execution model is inefficient when it suffers from the divergent control flow. The divergent execution paths across loop iterations take place sequentially on SIMD, which defeats part of the efficiency advantage of SIMD execution. This paper proposes a mechanism to compact the divergent branch threads to mitigate the impact of branch thread divergence on SIMD architectures. It relaxes the SIMD execution model by allowing the distinct instruction flows to be scheduled independently, instead of one single instruction flow. It increases flexibility and mitigates the synchronization cost of co-issuing instructions from different divergent branch threads by giving the Vector processing elements (VPEs) the ability to direct their own control flow. The proposed divergent branch threads compaction mechanism improves performance by 2.56x over traditional SIMD architecture for a wide variety of general purpose parallel applications while the area overhead only increases 6.48%.

A Low-Energy Wide SIMD Architecture with Explicit Datapath

Energy efficiency has become one of the most important topics in computing. To meet the ever increasing demands of the mobile market, the next generation of processors will have to deliver a high compute performance at an extremely limited energy budget. Wide single instruction, multiple data (SIMD) architectures provide a promising solution, as they have the potential to achieve high compute performance at a low energy cost. We propose a configurable wide SIMD architecture that utilizes explicit datapath techniques to further optimize energy efficiency without sacrificing computational performance. To demonstrate the efficiency of the proposed architecture, multiple instantiations of the proposed wide SIMD architecture and its automatic bypassing counterpart, as well as a baseline RISC processor, are implemented. Extensive experimental results show that the proposed architecture is efficient and scalable in terms of area, performance, and energy. In a 128-PE SIMD processor, the proposed architecture is able to achieve an average of 206 times speed-up and reduces the total energy dissipation by 48.3 % on average and up to 94 %, compared to a reduced instruction set computing (RISC) processor. Compared to the corresponding SIMD architecture with automatic bypassing, an average of 64 % of all register file accesses is avoided by the 128-PE, explicitly bypassed SIMD. For total energy dissipation, an average of 27.5 %, and maximum of 43.0 %, reduction is achieved.

A binary algorithm with low divergence for modular inversion on SIMD architectures

When performing modular arithmetic the most computationally expensive operation is the modular inversion of an integer. Its cost might be a problem for cryptanalytical applications (like the transformation from projective to affine coordinates within a Pollard rho algorithm implementation to solve the discrete logarithm problem on an elliptic curve) where performances constitute a key aspect. Good platforms for such operations are single-instruction multiple-data architectures, like graphic processing units (GPUs) because of their extremely competitive performance/price ratio. Unfortunately, when a single thread computes a single inversion, the whole computation on GPUs can be significantly slowed down in the presence of divergent threads. In this paper we describe a new algorithm to compute modular inversion on GPUs based on Stein’s Binary GCD. By exploiting the De Bruijn sequences and the Montgomery arithmetic, our version of Stein’s algorithm better fits GPUs, since it reduces the divergence among threads of the original algorithm. The paper includes a brief report on tests of our algorithm in six prime fields with characteristics of size ranging from 109 to 359 bits and in the two prime fields associated to the Mersenne primes \(2^{521} - 1\) and \(2^{607} - 1\).

Concurrent warp execution: improving performance of GPU-likely SIMD architecture by increasing resource utilization

Hardware parallelism should be exploited to improve the performance of computing systems. Single instruction multiple data (SIMD) architecture has been widely used to maximize the throughput of computing systems by exploiting hardware parallelism. Unfortunately, branch divergence due to branch instructions causes underutilization of computational resources, resulting in performance degradation of SIMD architecture. Graphics processing unit (GPU) is a representative parallel architecture based on SIMD architecture. In recent computing systems, GPUs can process general-purpose applications as well as graphics applications with the help of convenient APIs. However, contrary to graphics applications, general-purpose applications include many branch instructions, resulting in serious performance degradation of GPU due to branch divergence. In this paper, we propose concurrent warp execution (CWE) technique to reduce the performance degradation of GPU in executing general-purpose applications by increasing resource utilization. The proposed CWE enables selecting co-warps to activate more threads in the warp, leading to concurrent execution of combined warps. According to our simulation results, the proposed architecture provides a significant performance improvement (5.85 % over PDOM, 91 % over DWF) with little hardware overhead.

Eclat Algorithm for FIM on CPU-GPU co-operative & parallel environment

Extracting the frequent itemsets from a transactional database is a fundamental task in data mining field because of its broad applications in mining association rules, time series, correlations etc. The Apriori or Eclat approaches are the commonly used generate-and-check approach to obtain frequent itemsets from a database with a given threshold value. Implementations take advantage of the GPU's massively multi-threaded SIMD (Single Instruction, Multiple Data) architecture which will employ a bitmap data structure to represent vertical transaction list ,to exploit the GPU's SIMD parallelism , and to perform the support counting operation. The implementation runs entirely on the GPU and eliminates intermediate data transfer between the GPU memory and the CPU memory, which can reduce computation time and improve overall performance .OpenCL is a platform independent Open Computing Language for GPU computation. Thus, the aim of our approach is to develop efficient parallel new advanced Eclat strategy of Frequent Itemset Mining that utilize new-generation graphics processing units (GPUs) to speed-up the process.

Implementation of LTE system on an SDR platform using CUDA and UHD

In this paper, we present an implementation of a long term evolution (LTE) system on a software defined radio (SDR) platform using a conventional personal computer that adopts a graphic processing unit (GPU) and a universal software radio peripheral2 (USRP2) with a URSP hardware driver (UHD) to implement an SDR software modem and a radio frequency transceiver, respectively. The central processing unit executes C++ control code that can access the USRP2 via the UHD. We have adopted the Ettus Research UHD due to its high degree of flexibility in the design of the transceiver chain. By taking advantage of this benefit, a simple cognitive radio engine has been implemented using libraries provided by the UHD. We have implemented the software modem on a GPU that is suitable for parallel computing due to its powerful arithmetic and logic units. A parallel programming method is proposed that exploits the single instruction multiple data architecture of the GPU. We focus on the implementation of the Turbo decoder due to its high computational requirements and difficulty in parallelizing the algorithm. The implemented system is analyzed primarily in terms of computation time using the compute unified device architecture profiler. From our experimental tests using the implemented system, we have measured the total processing time for a single frame of both transmit and receive LTE data. We find that it takes 5.00 and 8.58 ms for transmit and receive, respectively. This confirms that the implemented system is capable of real-time processing of all the baseband signal processing algorithms required for LTE systems.

Efficient multimedia coprocessor with enhanced SIMD engines for exploiting ILP and DLP

Multimedia applications have become increasingly important in daily computing. These applications are composed of heterogeneous regions of code mixed with data-level parallelism (DLP) and instruction-level parallelism (ILP). A standard solution for a multimedia coprocessor resembles of single-instruction multiple-data (SIMD) engines into architectures exploiting ILP at compile time, such as very long instruction word (VLIW) and transport triggered architecture (TTA). However, the ILP regions fail to scale with the increased vector length to achieve high performance in the DLP regions. Furthermore, the register-to-register nature of SIMD instructions causes current SIMD engines to have limitations in handling memory alignment, data reorganization, and control flow. Many supporting instructions such as data permutations, address generations, and loop branches, are required to aid in the execution of the real SIMD computation instructions. To mitigate these problems, we propose optimized SIMD engines that have the capabilities for combining VLIW or TTA processing with a unified scalar and long vector computations as well as efficient SIMD hardware for real computation. Our new architecture is based on TTA and is called multimedia coprocessor (MCP). This architecture includes following features: (1) a simple coprocessor structure with 8-way TTA, (2) cost-effective SIMD hardware capable of performing floating-point operations, (3) long vector capabilities built upon existing SIMD hardware and a single register file and processor data path for both scalar operands and vector elements, and (4) an optimized SIMD architecture that addresses the SIMD limitations. Our experimental evaluations show that MCP can outperform conventional SIMD techniques by an average of 39% and 12% in performance for multimedia kernels and applications, respectively.

A flexible algorithm for calculating pair interactions on SIMD architectures

Calculating interactions or correlations between pairs of particles is typically the most time-consuming task in particle simulation or correlation analysis. Straightforward implementations using a double loop over particle pairs have traditionally worked well, especially since compilers usually do a good job of unrolling the inner loop. In order to reach high performance on modern CPU and accelerator architectures, single-instruction multiple-data (SIMD) parallelization has become essential. Avoiding memory bottlenecks is also increasingly important and requires reducing the ratio of memory to arithmetic operations. Moreover, when pairs only interact within a certain cut-off distance, good SIMD utilization can only be achieved by reordering input and output data, which quickly becomes a limiting factor. Here we present an algorithm for SIMD parallelization based on grouping a fixed number of particles, e.g. 2, 4, or 8, into spatial clusters. Calculating all interactions between particles in a pair of such clusters improves data reuse compared to the traditional scheme and results in a more efficient SIMD parallelization. Adjusting the cluster size allows the algorithm to map to SIMD units of various widths. This flexibility not only enables fast and efficient implementation on current CPUs and accelerator architectures like GPUs or Intel MIC, but it also makes the algorithm future-proof. We present the algorithm with an application to molecular dynamics simulations, where we can also make use of the effective buffering the method introduces.