Single Flux Quantum Logic Circuits Research Articles

A Local Optimization Method for Single Flux Quantum Logic Circuits Design Utilizing Synchronizer IPs

In the post-Moore era, slow-growing operating frequency and massive power dissipation make researchers seek new developing directions in integration circuits (ICs). The single flux quantum (SFQ) circuit, a type of superconducting digital circuit, is regarded as an alternative circuit for future computing technology. SFQ circuits are natural gate-level-pipelining synchronous sequential circuits requiring path balancing. However, path balancing may consume enormous resources, as the logic levels of fan-in gates of most gates are different, with the consumption originating from the extra gates (D-Flip-Flops, DFFs) for path balancing and the routing with a much larger clock tree. Hence, in this article, we propose a local optimization method to address the vast consumption problem of the clock tree caused by path balancing in SFQ circuits, primarily relying on self-developed electronic design automation tools for the JSICcomplier for SFQ circuits and using the SIMIT Nb03 cell library. Moreover, we design synchronizer IPs called Dsyn series to replace DFFs in path balancing. The clock nodes and the clocking path consumption are highly reduced by utilizing the proposed strategy, while the new series can be recognized as IPs and easily added to our library, affording scalability. Experiments in a demo S-box circuit demonstrated a percentage of Josephson junctions reduction in clock tree up to 36.48%, while on a few benchmark circuits, the corresponding results are up to 50.69%, demonstrating our method's effectiveness.

Margin and Yield Optimization of Single Flux Quantum Logic Cells Using Swarm Optimization Techniques

Single flux quantum (SFQ) logic family is an attractive alternative to CMOS technology with the promise of more than two–three orders of magnitude improvement in energy-delay product. However, component-level parameter variations that arise during the fabrication process of SFQ logic circuits tend to be very high, which means that the fabricated circuits may run into major functional and/or performance issues. Therefore, optimizing SFQ logic cells to maximize their operating parameter margins under different variability sources is required. In this article, a swarm optimization technique combining the best of automatic niching particle swarm optimization and fireworks algorithm is presented where the objective is to maximize the summation of the upper and lower bound margins over all design parameters of an SFQ logic cell. The proposed method eliminates all functional errors and improves the critical margin range and parametric yield values for six different logic cells by 22.83 and 15.22% on average, when compared to a previously optimized open-source cell library.

Braiding Operations for a Topological Josephson Junction Array using SFQ Current Pulses

Majorana bound states (MBSs) can occur in topological Josephson junction (JJ) arrays with the presence of a fractional vortex with 2π-phase winding. It has been theoretically shown that the braiding operation can be achieved by using current pulses, compatible with single flux quantum (SFQ) technology. Therefore, we designed an SFQ logic circuit for the braiding operations of the topological JJ array using single flux quanta in a conventional JJ array. Braiding operations could be realized by an SFQ logic circuit with double flux quantum driver. To obtain positive and negative current pulses using the SFQ logic circuit, we used SFQ logic circuits with ac biasing for simulation. Finally, we confirmed the CNOT operation using an array-type SFQ circuit by means of simulation and estimated the CNOT operation speed.

A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits With Maximum Path Length Consideration

In a single-flux-quantum (SFQ) circuit, almost all cells need to receive the clock signal that incurs a high clock routing overhead. Besides, the clock tree of an SFQ circuit requires the insertion of a clock splitter cell at every tree branching point that renders the conventional design flow of placement followed by clock tree synthesis (CTS) ineffective to obtain a high quality clock tree with low clock skew. Moreover, very few works in the literature attempted to minimize the maximum path length during SFQ circuit placement. The maximum path length, which is the length of the longest source-to-sink path of any data signal, should be minimized to achieve a higher final performance and to reduce the overhead for length matching in subsequent routing. To address these issues, we propose a two-stage global placement methodology and a placement refinement algorithm after placement legalization. Our two-stage global placement methodology first applies a conventional global placement algorithm to place the cells in the given SFQ circuit evenly, which is followed by CTS and clock splitter insertion, and then, performs a second stage of global placement to replace both the original cells and clock splitters at the same time. In the second global placement stage, the look-ahead legalization technique is used to spread out the original cells and the clock splitters, and the clock tree is resynthesized several times to obtain an optimized clock tree topology such that there are little overlaps of the clock splitters with the original circuit cells. We propose a novel net model in global placement that facilitates the concurrent optimization of the total wirelength and the maximum path length. After legalizing the placement of all cells, a specialized placement refinement method is run to further reduce the clock skew and the maximum path length. Compared with the previous state-of-the-art work, on average, we reduced the total half-perimeter wirelength by 9%, reduced the maximum path length by 58%, and reduced the clock skew by 32%.

Measurement and data-assisted simulation of bit error rate in RQL circuits

A circuit-simulation-based method is used to determine the thermally-induced bit error rate of superconducting Single Flux Quantum logic circuits. Simulations are used to evaluate the multidimensional Gaussian integral across noise current sources attached to the active devices. The method is data-assisted and has predictive power. Measurement determines the value of a single parameter, effective noise bandwidth, for each error mechanism. The errors in the distributed networks of comparator-free Reciprocal Quantum Logic nucleate across multiple Josephson junctions, so the effective critical current is about three times that of the individual devices. The effective noise bandwidth is only 6%–23% of the junction plasma frequency at a modest clock rate of 3.4 GHz, which is 1% of the plasma frequency. This analysis shows the ways measured bit error rate comes out so much lower than simplistic estimates based on isolated devices.

Demonstration of an efficient single flux quantum logic circuit by introducing a local magnetic flux biasing

We investigated local magnetic flux biasing (LFB) that induces a phase shift in superconductor circuits by locally applying a magnetic field through the superconductor loop with Josephson junctions. The arbitrary phase shift can be achieved using LFB without modifying the circuit fabrication process. To quantitatively evaluate the effects of introducing LFB for practical superconductor circuit applications, we designed a single flux quantum (SFQ) based non-destructive read-out flip-flop with complementary outputs (NDROC) and a delay flip-flop with complementary outputs (DFFC). The circuit area and static power consumption of the NDROC based on LFB architecture (LFB-NDROC) are approximately 67% and 36% of a conventional NDROC, respectively. The measured bias margin of the LFB-NDROC was in the range of 69%–129%. Using LFB, we were able to reduce the circuit area and power consumption for the DFFC by 67% and 83%, respectively. The measured bias margin of the DFFC with LFB was between 115% and 128%. LFB enabled us to implement a 5-to-32 SFQ decoder which comprises NDROC trees with a reduced circuit area of approximately 60% of a conventional decoder. The results obtained in this study can be applied to not just SFQ circuits but other superconductor circuits also, as they improve the area and power efficiency of such circuits.

Statistical analysis of error rate of large-scale single flux quantum logic circuit by considering fluctuation of timing parameters

The relationship between the timing margin and the error rate of the large-scale single flux quantum logic circuits is quantitatively investigated to establish a timing design guideline. We observed that the fluctuation in the set-up/hold time of single flux quantum logic gates caused by thermal noises is the most probable origin of the logical error of the large-scale single flux quantum circuit. The appropriate timing margin for stable operation of the large-scale logic circuit is discussed by taking the fluctuation of setup/hold time and the timing jitter in the single flux quantum circuits. As a case study, the dependence of the error rate of the 1-million-bit single flux quantum shift register on the timing margin is statistically analyzed. The result indicates that adjustment of timing margin and the bias voltage is important for stable operation of a large-scale SFQ logic circuit.

Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates

In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.

Observation of 0–π transition in SIsFS Josephson junctions

The 0–π transition in Superconductor-Insulator-superconductor-Ferromagnet-Superconductor (SIsFS) Josephson junctions (JJs) was investigated experimentally. As predicted by theory, an s-layer inserted into a ferromagnetic SIFS junction can enhance the critical current density up to the value of an SIS tunnel junction. We fabricated Nb′ | AlOx | Nb | Ni60Cu40 | Nb JJs with wedge-like s (Nb) and F (Ni60Cu40) layers and studied the Josephson effect as a function of the s- and F-layer thickness, ds and dF, respectively. For ds = 11 nm, π-JJs with SIFS-type jc(dF) and critical current densities up to jcπ=60 A/cm2 were obtained at 4.2 K. Thicker ds led to a drastic increase of the critical current decay length, accompanied by the unexpected disappearance of the 0–π transition dip in the jc(dF) dependence. Our results are relevant for superconducting memories, rapid single flux quantum logic circuits, and solid state qubits.

Fabrication of Submicrometer High Current Density ${\hbox{ Nb/Al-AlN}}_{\rm x}/{\hbox{ Nb}}$ Junctions

We have developed a sub-mum Nb/Al-AlNx/Nb Josephson junction and integrated circuit fabrication process using deep-UV lithography and inductively coupled plasma etch tools. The baseline process consists of 11 masking steps including ground plane, PdAu resistor, Nb/Al-AlNx/Nb trilayer, and two additional Nb wiring layers. The AlNx tunnel barriers are grown with plasma nitridation. These junctions exhibit low subgap leakage even at current densities exceeding 100 kA/cm2. The critical current spread of a series array of 50- kA/cm2, 0.6 mum diameter junctions is under 3%. For very high current density applications, these junctions are a good candidate to replace Nb/Al-AlOx/Nb junctions particularly in future generations of very high speed, rapid single flux quantum logic circuits. In this paper we discuss our baseline fabrication process and device characterization including junction capacitance extraction from direct measurements of the Josephson plasma frequency.

SFQ Pulse Transfer Circuits Using Inductive Coupling for Current Recycling

An increase in bias currents supplied to single-flux-quantum (SFQ) circuits is a rising problem in building large-scale integrated SFQ circuits, because the magnetic fields generated by bias currents and ground return currents affect the circuit operation. Current recycling technique, which can drastically reduce the total bias current of SFQ circuits, is expected to be a very effective solution for large-scale SFQ circuits. To realize the current recycling technique, signal transmission between SFQ logic circuits located on different ground planes is required. Two types of inductively coupled pulse transfer circuits were examined in this study. One is composed of a simple JTL driver and a DC-SQUID receiver whose junctions are slightly under-damped to enhance the magnetic sensitivity of the SQUID. The other circuit is composed of an SFQ driver based on a delay flip-flop (DFF) and a SQUID receiver. The advantage of the DFF-based circuit is that the coupling time between the driver and the receiver can be increased to ensure appropriate switching in the receiver junction. Two types of transfer circuits were implemented using the SRL 2.5 kA/cm2 Nb process and their correct operation was experimentally confirmed. Circuit structures for effective coupling of the SFQ pulse transfer were also investigated. It was shown that a ground plane boundary should be separated from a ground plane hole underneath coupling inductors to obtain high coupling factors.

Fabrication and operation of HTS SFQ logic circuits

High-temperature superconducting (HTS) single flux quantum logic circuits such as an inverter and an OR gate were designed. Circuit parameters were optimized for the HTS circuits to be successfully operated. The test circuits were fabricated by using the ramp-edge junction technology, and their logic operations were examined. The inverter was successfully operated at temperatures from 4.2K to 33K, and finite operating margins were observed in this temperature range. We also confirmed correct operation of the OR gate with dc supply current margins at temperatures from 40K to 50K.

Single-flux-quantum integer multiplier with systolic array structure

We propose an integer multiplier with systolic array structure for single-flux-quantum (SFQ) technology. Since SFQ logic circuits work by pulse logic, suitable circuit structure for SFQ logic circuits is different from one for semiconductor logic circuits. The systolic array is a circuit structure for VLSIs and consists of regularly arranged simple processing elements. All signals of the proposed systolic multiplier flow from input to output unidirectionally. This feature matches concurrent-flow clocking well. For evaluating the proposed systolic multiplier, we have designed a 4-bit systolic multiplier, as well as a 4-bit array multiplier which is one of the most typical parallel multipliers, and have compared them with each other. From the results of the design and the digital simulation, the number of Josephson junctions (JJs) of the 4-bit systolic multiplier is almost the half of that of the 4-bit array multiplier, and the latency of the former is about 1.5 times longer than that of the latter. Our estimation of the performance of larger-scale multipliers shows that the proposed systolic multiplier achieves comparable latency to the array multiplier, using extremely smaller number of JJs when the bit-width of input becomes large. We have fabricated a 1-bit cell of the systolic multiplier using NEC standard Nb process and have successfully tested it at low speed. The proposed systolic integer multiplier is attractive for SFQ technology.

Design and Investigation of Gate-to-Gate Passive Interconnections for SFQ Logic Circuits

We have developed a method of designing single-flux-quantum (SFQ) logic circuits with passive gate-to-gate interconnections. Based on our method, we designed a 2/spl times/2 switch in which all the interconnections are implemented with passive transmission lines (PTLs) while short Josephson transmission line (JTL) segments are used only to adjust the signal timings. Compared with an identical switch using JTL interconnections, the switch using PTL interconnections has 45% fewer wiring junctions and requires 48% less wiring power current. The switch operated at 40 GHz with a bias margin of /spl plusmn/9.5%.

Consideration of logic synthesis and clock distribution networks for SFQ logic circuits

In this paper we have considered how to perform logic synthesis of the single-flux-quantum (SFQ) logic circuits by using logic synthesis tools for semiconductor logic circuits. Fundamental difference of the SFQ logic gates from the semiconductor logic gates in terms of logic synthesis is that typical SFQ gates are clocked gate, where gates have to be clocked by SFQ pulses. In our approach, we divided the procedure into two steps; logic synthesis and clock distribution. In the logic synthesis step, the logic function is optimized using a logic synthesis tool without considering the clock network. The Design Analyzer provided from Synopsys is used in this study. We have developed an SFQ cell library for the logic synthesis. In the clock distribution step, clock networks for every clocked SFQ gates are designed taking account of timing. We used a clock-followed-data clocking scheme in this study. We have classified every clocked gate into stages, where the clocked gates in the same stage are clocked simultaneously. To demonstrate the validity of our approach, we have designed a controller of an 8-bit SFQ microprocessor.

Advanced Design Approaches for SFQ Logic Circuits Based on the Binary Decision Diagram

We will propose a new design approach for single-flux-quantum (SFQ) logic circuits based on a binary decision diagram (BDD). The BDD is a way to represent a logical function by using a directed graph, which is composed of nodes having one input (root) and two outputs (branches). The node has binary states internally which can be controlled from outside, and it switches a messenger entering from the root into one of two branches depending on the internal state. It has been proven that any combinational logic can be represented by this basic element. We will show that the BDD is effectively implemented by an SFQ circuit, where the node is replaced with an SFQ D/sub 2/ flip-flop. Important features of the BDD SFQ logic circuit are simplicity of circuit structure, self-timed nature and high modularity. We have designed a BDD SFQ adder and showed that the junction count and latency are smaller than that of the conventional RSFQ adder.

High-Speed Demonstration of Single-Flux-Quantum Cross–Bar Switch up to 50 GHz

We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.

A design approach to passive interconnects for single flux quantum logic circuits

We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTL's). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.

A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

High-Speed Operation of a Single-Flux-Quantum (SFQ) Cross/Bar Switch up to 35 GHz

Single-flux-quantum (SFQ) technology is a novel technology where binary information is represented by a single flux. It enables us to realize high-speed, low-power SFQ logic circuits, surpassing conventional complementary metal-oxide-silicon (CMOS) technology. We proposed an SFQ packet switch to avoid the bottlenecks in broadband networks of the future. To demonstrate high-speed operation of an SFQ logic circuit and its application to our switch architecture, we designed a cross/bar switch. It consists of 13 logic gates and 581 Josephson junctions were used in the layout. We confirmed correct operations up to 33 GHz in simulation. We placed the switch circuit in an on-chip test system for high-speed (over 10 GHz) test. Including I/O circuits, the system as a whole consists of 1236 Josephson junctions. The chip was fabricated by using NEC's standard Nb process. We carried out an on-chip test and found correct operations up to 35 GHz.