Single Flux Quantum Digital Circuits Research Articles

Process Control Monitoring for Fabrication Technology of Superconducting Integrated Circuits

We have developed a 6-kA/cm superconducting integrated circuit fabrication process toward large-scale single flux quantum digital circuits. To evaluate the process reliability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and tested. Fabrication parameters, for example, film thicknesses and etched depths of the layers, were measured by testing specific patterns during fabrication. Design parameters such as the critical current density J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> , normal-state resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> and actual sizes of Josephson junctions, the sheet resistance of Mo resistor R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sh</sub> , and the penetration depth of Nb films were evaluated by electrically characterizing PCM circuits after fabrication. We also monitored superconducting critical currents for vias and Nb lines, and insulation properties between the metal layers systematically.

Implementation of energy efficient single flux quantum digital circuits with sub-aJ/bit operation

We report the first experimental demonstration of recently proposed energy efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic, eliminating the dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ∼0.8 aJ/bit operation. Two types of demonstration eSFQ circuit, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA cm−2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.

100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process

A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm 2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5 kA/cm 2 to 10 kA/cm 2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400 GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100 GHz.

A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits

A method of sequential circuit synthesis is proposed for Single-Flux-Quantum (SFQ) digital circuits. Since all logic gates of SFQ digital circuits are driven by a clock signal, methods of sequential circuit synthesis for semiconductor digital circuits cannot derive the full power of high-throughput computation of SFQ circuit technology. In the method, a 'state module' consisting of a DFF and several AND gates is used. First, states of a sequential machine are encoded by one-hot encoding and state modules are assigned to the states one-by-one, and then, the modules are connected with each other according to the state transition. For the connection, Confluence Buffers (CBs), i.e., merger gates without clock signals are used. Consequently, gates driven by a clock signal are removed from its feedback loops, and therefore, a high-throughput SFQ sequential circuit is achieved. The experimental results on benchmark circuits show that compared with a conventional method for semiconductor digital circuits, the proposed method synthesizes circuits that work with 4.9 times higher clock frequency and have 17.3% more gates on average.

Internally shunted Josephson junctions with barriers tuned near the metal–insulatortransition for RSFQ logic applications

The fabrication of self-shunted SNS (superconductor/normal conductor/superconductor)Josephson junctions for rapid single flux quantum (RSFQ) logic couldpotentially facilitate increased circuit density, as well as reduced parasiticcapacitance and inductance over the currently used externally shunted SIS(superconductor/insulator/superconductor) trilayer junction process. We report thedeposition, fabrication, and device characterization of Josephson junctions prepared withNb1−yTiyN electrodesand TaxN barriers tuned near the metal–insulator transition, deposited on practical large-area oxide-bufferedsilicon wafers. When scaled to practical device dimensions, this type of junction is found to have anIcRn product of over 0.5 mV and a critical current(Ic) and normalresistance (Rn) of magnitudes suitable for single flux quantum digital circuits. A longer than expected normal-metal coherencelength (ξn) of 5.8 nm is inferred from the thickness dependence ofJc at 4.2 K for junctions fabricated using a barrier resistivity of13 mΩ cm. Althoughnot well understood and not quantitatively predicted by conventional theories, this results in a sufficientlyhigh Ic and IcRn to make the junctions suitable for practical applications. Similar observationsof unexpectedly large Josephson coupling currents in SNS junctions have beendocumented in other systems, particularly in cases when the barrier is near theM–I transition, and have become known as the giant proximity effect. The temperature dependence ofξn,IcRn,and Jc are also reported. For this technology to be used in practical applications, significantimprovements in our fabrication process are needed as we observe large variations inIc and Rn values across a 100 mm wafer, presumably as a result of variationsin the Ta:N stoichiometry and the resulting changes in theTaxN barrier resistivity.

Vision for single flux quantum very large scale integrated technology**This technology was exported from the United States in accordance with the USDepartment of Commerce Export Administration Regulations (EAR) for ultimatedestination in the United Kingdom. Diversion contrary to US law prohibited.

Single flux quantum (SFQ) electronics is extremely fast and has very low on-chip powerdissipation. SFQ VLSI is an excellent candidate for high-performance computing and otherapplications requiring extremely high-speed signal processing. Despite this, SFQ technologyhas generally not been accepted for system implementation. We argue that this is due, atleast in part, to the use of outdated tools to produce SFQ circuits and chips. Assuming theuse of tools equivalent to those employed in the semiconductor industry, we estimate thedensity of Josephson junctions, circuit speed, and power dissipation that could be achievedwith SFQ technology. Today, CMOS lithography is at 90–65 nm with about 20 layers.Assuming equivalent technology, aggressively increasing the current density above100 kA cm−2 to achieve junction speeds approximately 1000 GHz, and reducing device footprints by convertingdevice profiles from planar to vertical, one could expect to integrate about 250 M Josephson junctionscm−2 into SFQ digital circuits. This should enable circuit operation with clock frequencies above200 GHz and place approximately 20 K gates within a radius of one clock period. As aresult, complete microprocessors, including integrated memory registers, could befabricated on a single chip.

A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

Multilayer edge SNS SQUIDs for digital circuits

We have fabricated and characterized direct-injection High Temperature Superconducting (HTS) SQUIDs using a six-epitaxial-layer process which integrates edge geometry superconductor-normal-superconductor (SNS) junctions with an HTS ground plane. The period of the SQUID threshold curves was used to infer microstrip inductances of approximately 1 pH//spl square/ at 65 K. Total SQUID inductances as low as /spl ap/5 pH were inferred from the measured critical current modulation depth. A novel junction geometry was used in some devices to reduce the parasitic inductances of the junction leads by approximately 1 pH. Maintaining such low inductances is particularly important for Single Flux Quantum digital circuits.