Single Flux Quantum Circuits Research Articles

Quantum thermodynamics with a single superconducting vortex.

We demonstrate complete control over dynamics of a single superconducting vortex in a nanostructure, which we coin the Single Vortex Box. Our device allows us to trap the vortex in a field-cooled aluminum nanosquare and expel it on demand with a nanosecond pulse of electrical current. Using the time-resolving nanothermometry we measure [Formula: see text] joules as the amount of the dissipated heat in the elementary process of the single-vortex expulsion. Our experiment enlightens the thermodynamics of the absorption process in the superconducting nanowire single-photon detectors, in which vortices are perceived to be essential for a formation of a detectable hotspot. The demonstrated opportunity to manipulate a single superconducting vortex reliably in a confined geometry comprises a proof of concept of a nanoscale nonvolatile memory cell with subnanosecond write and read operations, which offers compatibility with quantum processors based either on superconducting qubits or on rapid single-flux quantum circuits.

Performance evaluation of superconductor integrated circuit simulators

The development of superconductor integrated circuits (SCIC) places increasing demands on electronic design automation (EDA) tools. Circuit simulation is a crucial step in the design process of superconducting quantum interference devices (SQUID) and single flux quantum (SFQ) circuits. Over the years, there have been many SC circuit simulators, like JSPICE, JSIM, WRspice, JoSIM, PSCAN2, JSICsim, PrimeSim HSPICE, Spectre, and more. The previous studies have compared the differences in results among some simulators for the same circuit cases. However, designers of SC circuits still face challenges when choosing simulators and setting simulation parameters. The performance of these simulators lacks comprehensive and quantitative evaluations to date. To evaluate the performance of the simulators, we focused on three aspects: the differences among the IV results, accuracy, and speed. For characterizing the accuracy of the simulators, we proposed a method that uses the relative error between the numerical and analytical solutions at the L-C resonance point on the IV curve of a dc SQUID. In this article, we have selected five representative simulators JoSIM, JSIM, WRspice, PSCAN2, and JSICsim for our study. By using multiple cases of the bare and coupled dc SQUID, multiple IV curves, and the analytical solution as a reference, we comprehensively compared the performance of these simulators. Additionally, we quantitatively examined the impact of two key simulation parameters, namely, the maximum allowed simulation timestep (max timestep) and relative tolerance (RelTol), on the performance of these simulators. Our results show that the normalized voltage differences in the IV curves of different simulators are relatively small (within 0.06) in regions far from the L-C resonance point, while they increase significantly near the L-C resonance point (maximum is 0.4). PSCAN2 exhibits a significant relative error of approximately 16% when the max timestep is 0.6ps and RelTol is 1×10−1, which is close to its default RelTol value. Our work provides some insights and references for the designers of SC circuits on how to choose simulators and set simulation parameters.

Hybrid synaptic structure for spiking neural network realization

Neural networks and neuromorphic computing represent fundamental paradigms as alternative approaches to Von-Neumann-based implementations, advancing in the applications of deep learning and machine vision. Nonetheless, conventional semiconductor circuits encounter challenges in achieving ultra-fast processing speed and low power consumption due to their dissipative properties. Conversely, single flux quantum circuits exhibit inherent spiking behavior, showcasing their characteristics as a promising candidate for spiking neural networks (SNNs). In this work, we present a compact hybrid synapse circuit to mimic the biological interconnect functionality, enabling the weighting operations for excitatory and inhibitory impulses. Additionally, the proposed structure facilitates input accumulation, which is performed before the activation function. In the experiments, our synaptic structure interfaces with a soma circuit fabricated using a commercial Nb process, underscoring its compatibility and supporting its potential for integration into efficient neural network architectures. The weight value on the synapse is configurable by utilizing cryo-CMOS circuits, providing adaptability to the inference networks. We’ve successfully designed, fabricated, and partially tested the JJ-Synapse within our cryocooler system, enabling high-speed inference implementation for SNNs.

Simulations of superconducting quantum gates by digital flux tuner for qubits

Abstract The interconnection bottleneck caused by limitations of cable number, inner space and cooling power of dilution refrigerators has been an outstanding challenge for building scalable superconducting quantum computers with the increasing number of qubits in quantum processors. To surmount such an obstacle, it is desirable to integrate qubits with quantum–classical interface (QCI) circuits based on rapid single flux quantum (RSFQ) circuits. In this work, a digital flux tuner for qubits (DFTQ) is proposed for manipulating flux of qubits as a crucial part of the interface circuit. A schematic diagram of the DFTQ is presented, consisting of a coarse tuning unit and a fine-tuning unit for providing magnetic flux with different precision to qubits. The method of using DFTQ to provide flux for gate operations is discussed from the optimization of circuit design and input signal. To verify the effectiveness of the method, simulations of a single DFTQ and quantum gates including a Z gate and an iSWAP gate with DFTQs are performed for flux-tunable transmons. The quantum process tomography corresponding to the two gates is also carried out to analyze the sources of gate error. The results of tomography show that the gate fidelities independent of the initial states of the Z gate and the iSWAP gate are 99.935% and 99.676%, respectively. With DFTQs inside, the QCI would be a powerful tool for building large-scale quantum computers.

High area efficiency binary neural processing elements with time-domain signals using SFQ circuits

With the increasing processor performance requirements of convolutional neural networks, we believe that research on superconducting neural networks based on single flux quantum (SFQ) circuits holds significant potential. However, the typical multiply and accumulate operations used in neural networks often lead to a significant increase in circuit area due to the limitations of the integration density of the current SFQ circuit fabrication process. In this work, we propose a binary neural processing element (PE) that utilizes time-domain signal expression. Time-domain signals express multi-bit binary data in time information, which reduces the number of data lines to decrease the circuit area. In the proposed binary neural PE, multiplication is achieved through exclusive-NOR gates and addition is realized by controlling the delay of time-domain signals. We designed and simulated a 3 × 3 convolution circuit using 10 Nb layer process with a critical current density of 10 kA cm−2. Compared to the convolution circuit implemented using conventional SFQ logic, the proposed circuit reduces the number of Josephson junctions by approximately 56% and decreases the area by about 60%.

Research on the current compensation mechanism of FJTL in ERSFQ

Energy-efficient rapid single flux quantum (ERSFQ) devices have unique energy advantages with a power consumption of less than 0.001fJ per single-bit switch, even considering the energy required for the refrigeration system, achieving ultra-low energy consumption of sub-fJ/bit. Combined with its typical operating frequency in the tens of GHz range, ERSFQ circuits have the potential to realize computing chips with extremely high computational power and energy efficiency, making them highly promising for applications in the post-Moore era. However, the performance improvement of ERSFQ circuits faces two challenges. One is how to reduce the size of their feeding Josephson transmission line (FJTL), which is required to stabilize the voltage bias of the ERSFQ circuits. The second challenge is how to improve their bias margin. The measured bias margin of ERSFQ circuits is relatively smaller than for Rapid Single Flux Quantum (RSFQ) circuits. This study investigates the current compensation mechanism of the FJTL and derives a formula for the compensating current ΔI in the main logic circuit by each pulse input to the FJTL. Based on the formula, a method is proposed to enhance the bias margin of ERSFQ circuits while reducing the size of FJTL by applying feeding pulses into the FJTL. We applied this method to an 8-bit ERSFQ shift register (SR), where the size of its FJTL is 4 JTLs (each JTL consists of 2 Josephson junctions). The measurement demonstrated an improvement of the bias margin from [84 %, 104 %] to [38 %, 104 %], confirming the feasibility of the proposed method. Furthermore, by comparing the measurement results of an 8-bit ERSFQ SR, where the size of its FJTL is 6 JTLs, it is demonstrated that applying this method can also reduce the size of the FJTL while maintaining a large margin.

Side-Channel Leakage in SFQ Circuits and Related Attacks on Qubit Control and Readout Systems

Single flux quantum (SFQ) technology is currently used as a cryogenic control and readout circuitry of superconducting quantum computers. The low power operation and high switching frequency of SFQ technology are instrumental to efficiently scale a quantum computer. With the growing interest in the hardware security of SFQ circuits, a novel side-channel leakage mechanism in SFQ-to-DC converters is uncovered in this paper. The leakage mechanism is investigated for two logic styles, namely rapid SFQ (RSFQ) and energy-efficient RSFQ (ERSFQ). By observing the fluctuations in the power supply provided by the room temperature electronics, a malicious adversary can extract critical information about the applied input signals. This type of side-channel leakage can lead to serious security vulnerabilities for superconducting electronics and quantum computers. Two potential side-channel attacks that exploit this vulnerability and target SFQ-based qubit control and readout systems are proposed.

Qubit energy tuner based on single flux quantum circuits

A device called the qubit energy tuner (QET), based on single flux quantum (SFQ) circuits, has been proposed for Z control of superconducting qubits. The QET is created by improving flux digital-to-analog converters (flux DACs). It can set the energy levels or frequencies of qubits, particularly flux-tunable transmons, and perform gate operations requiring Z control. The circuit structure of the QET is elucidated, consisting of an inductor loop and flux bias units for coarse or fine-tuning. The key feature of the QET is analyzed to understand how SFQ pulses change the inductor loop current, which provides external flux for qubits. Three simulations were performed to verify QET functionality. The first simulation verified the responses of the inductor loop current to SFQ pulses, showing a relative deviation of approximately 4.259% between the analytical solutions of the inductor loop current and the solutions from the WRSpice time-domain simulation. The second and third simulations, using QuTip, demonstrated how to perform a Z gate and an iSWAP gate using the QET, respectively, with corresponding fidelities of 99.99884% and 99.93906% for only one gate operation to specific initial states. These simulations indicate that the SFQ-based QET could act as an efficient component of SFQ-based quantum–classical interfaces for digital Z control of large-scale superconducting quantum computers.

Fabrication Process for Monolithic Integration of a Nitride Superconductor-Based Superconducting Qubit with a Single Flux Quantum Control Circuit

We developed a process for fabricating nitride superconductor-based superconducting qubits monolithically integrated with a single flux quantum (SFQ)-based readout and control circuits. Since we used a Josephson junction (JJ) made of an NbN/AlN/NbN tri-layer, including a critical current density ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) of 50 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> as the suitable material for superconducting qubits and SFQ readout/control circuits operating at 20 mK, the JJs for both the qubits and the SFQ circuits could simultaneously be fabricated. The device structure was also composed of three superconductive layers, comprising two superconductive layers as wiring layers and other layers as the top ground plane. Then, we used a Pd film as the resistive layer, which is required as the shunt resistors and the bias resistors for the SFQ control circuits, followed by an investigation of the properties of NbN/AlN/NbN epitaxial junctions and evaluation of the sheet inductance of the base NbN and wiring NbTiN layer. Our results showed the successful fabrication of a JJ with a sufficiently low leakage current and a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> of around 50 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which was close to the target value. Furthermore, the evaluated sheet inductance exceeded 1 pH, which was several times larger than the values obtained for Nb-integrated circuits.

Stripline Topology for Flux Mitigation

The increasing complexity of modern single flux quantum (SFQ) circuits has increased the importance of flux trapping and trapped magnetic fields within SFQ systems. This trapped flux reduces margins while damaging the operability of superconductive circuits. In this paper, an area efficient stripline topology is introduced to prevent flux from being trapped within striplines. The topology is composed of coupled narrow lines rather than wide striplines. The proposed topology uses a fingered narrow line configuration. The fingered narrow line topology enhances the scalability of SFQ systems while not requiring additional area. The proposed topology decreases the length of the striplines by exploiting the mutual inductance between narrow parallel lines. The topology requires less area while preventing flux from being trapped within wide superconductive striplines. Due to the configuration of the proposed stripline, residual current is eliminated in VLSI complexity SFQ circuits. The fingered narrow line topology also reduces coupling capacitance between striplines. The proposed topology is compatible with automated routing of large scale SFQ integrated circuits.

Design and Fabrication of Low-Power Single-Flux-Quantum Circuits Toward Quantum Bit Control

we report low-power single-flux-quantum (SFQ) circuits fabricated with a lowered critical current density process and low-voltage design. We selected 250 A/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> to obtain 2–10 μA Josephson junctions (JJs) easily using conventional facilities. Our numerical simulation shows that the expected operating frequency is 10 GHz and that we can reduce the bias voltage to 0.1–0.5 mV; power consumption can be reduced to around 1 nW per JJ. We newly developed a fabrication process featuring four planarized Nb layers and a Pd resistor layer. We obtained the correct operation of several basic SFQ circuit elements designed with the lowered critical currents to 1/2 of the conventional circuits at 4.2 K. We also evaluated the Josephson junction critical currents, specific capacitance, resistance, and inductance at 3 K and 300 mK. We observed an increase of 7% in the critical currents at 300 mK, while the other parameters were unchanged. We demonstrated a 0.5-mV Josephson transmission line where we lowered the critical currents to 1/10. We expect such low-power SFQ circuits to operate at 20 mK, providing classical, general-purpose digital processing near quantum bits.

Demonstration and Comparison of On-Chip High-Frequency Test Methods for RSFQ Circuits

On-chip high-frequency test for Rapid Single Flux Quantum (RSFQ) circuits without external high-frequency equipment is very attractive and promising. The test method based on Shift Register (SR) is widely used for long time. Recently, we have proposed two test methods based on Pseudo Random Binary Sequence (PRBS) generator. In this paper, a Full Adder (FA) is taken as an example of circuit under test and the design methodology of the above approaches is presented. For FA with the traditional and two proposed approaches, the high-frequency test circuits are fabricated and tested. We demonstrate the successful measurement of the three circuits with the maximum operating frequency of the full adder at 23.3 GHz, 26.2 GHz and 27.4 GHz respectively. Based on the experimental results, the clock frequency measurement in the proposed two PRBS based test systems is more accurate and time-saving, which is advantageous for high-frequency RSFQ circuits measurement.

Wire Length-Matching Aware Placement Method for Rapid Single Flux Quantum Logic Circuits

This paper proposes a fast automatic gate placement method for gate-level-pipelined Rapid Single Flux Quantum (RSFQ) circuits that are designed to have a high throughput. In such circuits, the gates in a pipeline stage are placed in a column and wires are routed in the area between adjacent columns. In wire routing, wire length-matching is performed. The proposed method performs gate placement for a given netlist to minimize the sum of the maximum distance between connected gates in each pair of adjacent columns. It leads to short wire extensions in wire length matching for increasing the operation frequency and small circuit area. The proposed method consists of a recursive procedure including two placements, selecting a pivot column, and determining the gate placement in the pivot column. The netlist is divided into two netlists with the pivot column. The recursive procedure performs gate placements for the two divided netlist. It is repeated until the location of every gate is determined. We implemented a placement tool by the proposed method and performed the gate placement for three circuits including several hundreds of gates. The proposed placement was 14 to 40 times faster than a placement based on simulated annealing where the sum of the maximum distance between connected gates is approximately the same.

60-GHz Single Flux Quantum Pulse Transfer Circuit for Serial Biasing

Serial Biasing (SB) is a technique to reduce the total DC bias current of Rapid Single Flux Quantum (RSFQ) circuits by partitioning a design into several islands with isolated grounds and sequential biasing. In this paper we focus on the design of a driver-receiver pair (DRP) to transfer pulses between islands that are galvanically isolated for pulse streams. We discuss both DRP itself and the structure for its testing, that comprises several DRPs connected in series, on-chip pseudo random binary sequence (PRBS) generator for circuit stimulation, and HF output interface. We use the layout of DRPs’ chain as an example to illustrate the advantage of the grapevine (GV) approach, introduced earlier, to manage the bias current flowing into and out of an island. The GV current management technique is analyzed by both electromagnetic simulations and measurement, compared, and contrasted with the so-called ‘straightforward’ (SF) approach. The maximum operational frequency for SF test structure was 10 GHz with zero margins for the SB current. Measurements of the GV structure at 10 GHz demonstrated BER of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> with ±5.8% margins for SB current. We observed the correct operation of the 5-island DRP chain up to 60 GHz using the grapevine approach for SB current management. All chips were fabricated at MIT Lincoln Laboratory using SFQ5ee fab node.

Golden Bump Based Flip-Chip Interconnection for Superconducting Multi-Chip Module

This paper introduces the preparation of golden bumps on the single flux quantum (SFQ) circuit chip by using the 20-μm-diameter golden wire and the flip-chip (FC) bonding of the SFQ chip and the substrate by the ultrasonic bonding method. Firstly, a coplanar waveguide (CPW) flip-chip interconnect structure was designed and fabricated, and the low-temperature transmission performance i.e., S-parameters were tested. The results showed that <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S₁₁</i> ≤ -10 dB and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S₂₁</i> ≥ -3 dB among the range from 100MHz to 52 GHz at 4.2 K. And the golden bump can transmit PRBSs of 5 Gbps, and its bit error rate (BER) is less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . Secondly, the flip-chip bonded SFQ driver& receiver circuits with 4.7-Ohm impedance were prepared and the BER of the SFQ pulse signals were measured by the driver& receiver circuits. The test results showed a zero-bit error rate when the number of transmitted codes is in the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . The experimental results show that the golden bump based flip-chip interconnection has good high-frequency transmission performance, and can be used for high-bandwidth and narrow pulse signal transmission in superconducting multi-chip modules (MCMs).

Influence of surrounding vortices on critical current of a Nb/Al-AlO x /Nb Josephson junction

Resistively shunted Nb/Al-AlO x /Nb Josephson junctions have been widely used in large-scale superconducting electronics such as the single-flux quantum circuit. The critical current primarily determines the working margin of the circuit. The distribution of vortices in the niobium film around superconducting devices is also commonly suspected to degrade the performance of devices. Unfortunately, most studies on Nb/Al-AlO x /Nb Josephson junctions only present electric transport measurements. Using a magnetic force microscope, we observed the static distribution of the vortices around the junction after sweeping the current–voltage curves of the junction in-situ. The measurements showed that the distribution density of vortices affected the critical current of the junction. Furthermore, we observed an aggregation of vortices arising from the Joule heat generated by the shunt resistor. This caused an irreversible decrease in the junction’s critical current.

High density fabrication process for single flux quantum circuits

We implemented, optimized, and fully tested a superconducting Josephson junction fabrication process over multiple runs tailored for integrated digital circuits that are used for control and readout of superconducting qubits operating at millikelvin temperatures. This process was optimized for highly energy efficient rapid single flux quantum (ERSFQ) circuits with critical currents reduced by a factor of ∼10 as compared to those operated at 4.2 K. Specifically, it implemented Josephson junctions with 10 μA unit critical current fabricated with 10 μA/μm2 critical current density. In order to circumvent the substantial size increase in the SFQ circuit inductors, we employed an NbN high kinetic inductance layer with 8.5 pH/sq sheet inductance. Similarly, to maintain the small size of junction resistive shunts, we used a non-superconducting PdAu alloy with 4.0 Ω/sq sheet resistance. For integration with quantum circuits in a multi-chip module, 5 and 10 μm height bump processes were also optimized. To keep the fabrication process in check, we developed and thoroughly tested a comprehensive process control monitor chip set.

Coherence-limited digital control of a superconducting qubit using a Josephson pulse generator at 3 K

Compared to traditional semiconductor control electronics (TSCE) located at room temperature, cryogenic single flux quantum (SFQ) electronics can provide qubit measurement and control alternatives that address critical issues related to scalability of cryogenic quantum processors. Single-qubit control and readout have been demonstrated recently using SFQ circuits coupled to superconducting qubits. Experiments where the SFQ electronics are co-located with the qubit have suffered from excess decoherence and loss due to quasiparticle poisoning of the qubit. A previous experiment by our group showed that moving the control electronics to the 3 K stage of the dilution refrigerator avoided this source of decoherence in a high-coherence three-dimensional transmon geometry. In this paper, we also generate the pulses at the 3 K stage but have optimized the qubit design and control lines for scalable two-dimensional transmon devices. We directly compare the qubit lifetime T1, coherence time T2*, and gate fidelity when the qubit is controlled by the Josephson pulse generator (JPG) circuit vs the TSCE setup. We find agreement within the daily fluctuations for T1 and T2*, and agreement within 10% for randomized benchmarking. We also performed interleaved randomized benchmarking on individual JPG gates demonstrating an average error per gate of 0.46% showing good agreement with what is expected based on the qubit coherence and higher-state leakage. These results are an order of magnitude improvement in gate fidelity over our previous work and demonstrate that a Josephson microwave source operated at 3 K is a promising component for scalable qubit control.

Single-flux-quantum signal processors monolithically integrated with a superconducting nanostrip single-photon detector array

We developed a monolithic integration process for a superconducting nanostrip single-photon detector (SNSPD) and a cryogenic signal processor based on a single-flux-quantum (SFQ) circuit. Sixteen-pixel SNSPDs consisting of a 10-nm-thick and 100-nm-wide NbTiN nanowire were fabricated on a 3-in. Si wafer with an SFQ merger fabricated by the National Institute of Advanced Industrial Science and Technology Nb 2.5 kA/cm2 standard process 2. Subsequently, we illuminated the photons on the 16-pixel SNSPD array through an optical fiber and obtained a similar bias-current dependence of the detection efficiency with a single-pixel SNSPD without the SFQ merger. This indicates that the SFQ merger works correctly, and that the power dissipation of the SFQ circuit, which is estimated to be 200 μW, does not deteriorate the photon detection of SNSPD fabricated on the same chip with a size of 5 × 5 mm2. Furthermore, we measured timing jitter using a pulsed laser as the photon source. Owing to the careful tuning of the wiring length between each pixel of the 16-pixel SNSPD and each input port of the SFQ merger, the obtained timing jitter was 41.4 ps, which is approximately equal to or less than that of the single-pixel SNSPD.

Chemical mechanical planarization for Ta-based superconducting quantum devices

We report on the development of a chemical mechanical planarization (CMP) process for thick damascene Ta structures with pattern feature sizes down to 100 nm. This CMP process is the core of the fabrication sequence for scalable superconducting integrated circuits at a 300 mm wafer scale. This work has established the elements of various CMP-related design rules that can be followed by a designer for the layout of circuits that include Ta-based coplanar waveguide resonators, capacitors, and interconnects for tantalum-based qubits and single flux quantum circuits. The fabrication of these structures utilizes a 193 nm optical lithography along with 300 mm process tools for dielectric deposition, reactive ion etch, wet-clean, CMP, and in-line metrology—all tools typical for a 300 mm wafer CMOS foundry. Theprocess development was guided by measurements of the physical and electrical characteristics of the planarized structures. Physical characterization such as atomic force microscopy across the 300 mm wafer surface showed that local topography was less than 5 nm. Electrical characterization confirmed low leakage at room temperature, and less than 12% within wafer sheet resistance variation for damascene Ta line widths ranging from 100 nm to 3 μm. Run-to-run reproducibility was also evaluated. Effects of process integration choices including the deposited thickness of Ta are discussed.