Single Event Functional Interrupts Research Articles

Electron-Induced Single-Event Effect in 28 nm SRAM-Based FPGA

As the feature size of integrated circuit decreases, the critical charge of single-event effect decreases as well, making nano-scale devices more susceptible to the high-energy charged particles during their application in space. Here, we study the electron-induced single-event effect in 28 nm static random-access memory (SRAM)-based field programmable gate array (FPGA) utilizing high-energy electrons with energy of 1 MeV~5 MeV. The experimental results demonstrate that the 3 MeV electrons can cause single-event functional interrupts (SEFIs) in FPGA, while the electrons with other energies cannot. To further explore the mechanism of electron-induced SEFIs in this nanoscale FPGA, we combined Monte Carlo, Technology Computer-Aided Design (TCAD), and Simulation Program with Integrated Circuit Emphasis (SPICE) simulations. It is revealed that the SEFI was mainly caused by the direct ionization effect of high-energy electrons, and the SEFI was related to the interactions between multiple sensitive nodes.

Investigation of Single-Event Effects for Space Applications: Instrumentation for In-Depth System Monitoring

Ionizing radiation induces the degradation of electronic systems. For memory devices, this phenomenon is often observed as the corruption of the stored data and, in some cases, the occurrence of sudden increases in current consumption during the operation. In this work, we propose enhanced experimental instrumentation to perform in-depth Single-Event Effects (SEE) monitoring and analysis of electronic systems. In particular, we focus on the Single-Event Latch-up (SEL) phenomena in memory devices, in which current monitoring and control are required for testing. To expose the features and function of the proposed instrumentation, we present results for a case study of an SRAM memory that has been used on-board PROBA-V ESA satellite. For this study, we performed experimental campaigns in two different irradiation facilities with protons and heavy ions, demonstrating the instrumentation capabilities, such as synchronization, high sampling rate, fast response time, and flexibility. Using this instrumentation, we could report the cross section for the observed SEEs and further investigate their correlation with the observed current behavior. Notably, it allowed us to identify that 95% of Single-Event Functional Interrupts (SEFIs) were triggered during SEL events.

Radiation-Tolerant Deep Learning Processor Unit (DPU)-Based Platform Using Xilinx 20-nm Kintex UltraScale FPGA

This paper presents a platform and design approach for enabling radiation-tolerant deep learning acceleration on SRAM-based 20nm Kintex UltraScale™ FPGAs, for terrestrial and high-radiation environments. The presented platform is suitable for deep neural network (DNN) implementations with an emphasis on image classification and includes solutions to mitigate both radiation-induced Single Event Functional Interrupts (SEFIs) and network datapath corruptions. The radiation-tolerant deep learning platform combines Xilinx’s Deep Learning Processing Unit (DPU) IP, Triple Modular Redundancy (TMR) MicroBlaze soft processor IP and Soft Error Mitigation (SEM)-IP to mitigate SEFIs. Furthermore, a technique known as Fault Aware Training (FAT) was applied to effectively mitigate single event effects in the datapath. Test results from a high-energy proton beam (> 60 MeV) experiment using the ResNet-18 Convolutional Neural Network (CNN) for image classification are presented. The Single Event Upset (SEU) rate, system-level SEFI rate and neural network classification/datapath performance are compared between the radiation-tolerant platform and a standard, non-mitigated approach. Results show that datapath classification errors dominate the system response (90%) vs. SEFIs (10%). When compared to standard non-mitigated training techniques, the radiation-tolerant platform using fault aware training methods shows dramatic improvements in overall system response: the overall single event cross-section was reduced by half and 40% reduction in misclassification errors were observed. Also, datapath events with classification accuracy degradation larger than 5% were completely mitigated. The SEFI rate was reduced by 100X with implemented solutions and can be further reduced by optimizing the physical separation between TMR modules.

Assessment of Radiation Effects on Attitude Estimation Processing for Autonomous Things

This article investigates and assesses neutron radiation effects on attitude estimation (AE) processing, typically embedded in inertial navigation systems (INSs) and upcoming autonomous things. Findings highlight the importance of radiation-induced critical failures that can upset the on-board AE processing and consequently the inertial navigation. Radiation tests and analyses were conducted by considering as on-board AE processing the execution of classical AE algorithm on multi-core computer hardware exposed to 14-MeV neutron and thermal neutron radiation. Three computing strategies and different case-study scenarios were tested and compared. Results suggest that the contribution of radiation-induced soft errors to be mitigated on the embedded AE processing is essentially related to single-event functional interrupts (SEFIs) that can lead the inertial navigation to critical failures.

Measurement and evaluation of the Single Event Effects of high-performance SerDes circuits

This paper characterizes the Single Event Effect (SEE) sensitivities of the Serializer/Deserializer (SerDes) module on the advanced 28 nm Xilinx Kintex-7 Field Programmable Gate Array (FPGA). A systematical SEE measurement method is proposed and implemented to evaluate the SEE sensitivity of the SerDes circuits. In our experiments, an extremely low Single Event Upset (SEU) Linear Energy Transfer (LET) threshold of the SerDes circuits was investigated, and both the recoverable and unrecoverable Single Event Functional Interrupts (SEFIs) were clearly distinguished and classified. In the experiments, it was found that the SEUs and recoverable SEFIs of the TX and RX in the same channel were closely related due to their shared clock and control circuits. Based on this detailed survey, a further discussion of the mechanisms of the SEU, recoverable SEFI, and unrecoverable SEFI is also provided. The SEE sensitivity of the high-speed SerDes circuits presented in this paper will promote the effective utilization of error mitigation strategies in order to control the risks of applications in radiation environments.

A Methodology to Analyze the Fault Tolerance of Demosaicking Methods against Memory Single Event Functional Interrupts (SEFIs)

Electronic circuits in harsh environments, such as space, are affected by soft errors produced by radiation. A single event functional interrupt (SEFI) can affect the behavior of a memory chip, with one or more rows, columns or even the whole device producing a wrong value when reading a set of stored bits. This problem may affect raw Bayer images stored in satellites and other spacecraft. In this paper, we present a methodology to analyze how different interpolation algorithms behave when they try to reconstruct the affected Bayer images into standard red, green and blue (RGB) images. This methodology can be used to compare and develop new fault-tolerant algorithms. The proposed methodology has been illustrated by studying a subset of interpolation algorithms. The results obtained from this example show that the interpolation algorithms that traditionally offer better results in a normal operation (in the absence of errors) are not always the best when SEFI errors are present in the Bayer images.

SEU Characterization of Three Successive Generations of COTS SRAMs at Ultralow Bias Voltage to 14.2-MeV Neutrons

This paper presents a single event upset (SEU) sensitivity characterization at ultralow bias voltage of three generations of commercial off-the-shelf static random access memories (SRAMs) manufactured in 130-, 90-, and 65-nm CMOS processes. For this purpose, radiation tests with 14.2-MeV neutrons were performed for SRAM power supplies ranging from 0.5 to 3.15 V. The experimental results yielded clear evidences of the SEU sensitivity increase at very low bias voltages. These results have been cross-checked with predictions issued from the modeling tool multiscales single event phenomena predictive platform. Large-scale single event latchups and single event functional interrupts (SEFIs), observed in the 90- and 130-nm SRAMs, respectively, are also presented and discussed.

FFI4SoC: a Fine-Grained Fault Injection Framework for Assessing Reliability against Soft Error in SoC

Recently, system-on-chips (SoCs) are increasingly employed in reliable applications for their high-performance and high-densities. Moreover, the structure shrinking of SoC leads to its proneness to radiation-induced soft errors. This paper presents a fine-grained fault injection framework for SoC (FFI4SoC) to assess the reliability of SoC against soft errors. FFI4SoC facilitates fault injection for SoC by defining the primary components and rules that are required by fine-grained fault injection. Furthermore, based on FFI4SoC, we develop a fine-grained fault injection tool named SSIFFI for bare-metal MicroZed. The design of SSIFFI is presented in order to illustrate the application of FFI4SoC. Finally, SSIFFI is engaged in simulated fault injection experiments to explore the cause of single event functional interrupts (SEFIs) and to validate functional properties of FFI4SoC. The experimental results disclose detailed reasons for SEFI and prove that FFI4SoC can be employed to assess reliability of SoC well with the merit of fine-grained injection.

Experimental study about single event functional interrupt of ferroelectric random access memory induced by 30-90 MeV proton

Ferroelectric random access memory (FRAM) is a promising memory for space application. The performance of FRAM under irradiation environment should be investigated, especially under proton irradiation environment, which dominates the particles in the space environment. The experiments on single event effects are carried out for two types of FRAMs (FM22L16 and FM28 V100) based on the proton cyclotron of China institute of atomic energy. Both dynamic and static mode are tested for each chip under the irradiation of proton in an energy range from 30 MeV to 90 MeV. Single event upsets (SEUs) and single event functional interrupts (SEFIs) are observed only on FM22L16, where the SEFI is recorded as a significantly transient error with or without memory cell upsets. The SEFI can be subdivided into soft SEFI and hard SEFI according to whether those significantly transient errors disappear or not when the irradiation is paused. Single event effect performances of FM22L16 are accurately described, and the SEFI cross section in an energy range from 50 MeV to 90 MeV is obtained experimentally. The cross section of SEFI increases with proton energy increasing and reaches 10<sup>-3</sup>/cm<sup>2</sup> at 90 MeV. To further study the mechanism of SEFI, the pulsed laser beam with a wavelength of 1064 nm is used to pinpoint the sensitive area of SEFI in the FRAM. Pulsed laser experiment is easy to carry out when single pulsed laser radiates on the device from the back side. Results show that a certain part in peripheral circuit is detected as a sensitive area to SEFI. The sensitive area could be a register or buffer which is vulnerable to irradiation. Only SEUs are observed when the pulsed laser radiates others area of peripheral circuit and memory cell. A hypothesis that a micro latch-up in the CMOS-based peripheral circuit leads to the SEFI is proposed to explain the test results, for the CMOS-based peripheral circuit is sensitive to irradiation. The further reason is the energy deposition in silicon substrate by protons with energies ranging from 30 MeV to 90 MeV through nuclear reaction, which triggers the silicon controlled rectifier structure in the FRAM peripheral circuit. According to the hypothesis, a transient current should be generated in the peripheral circuit when the micro latch-up happens. The transient current is observed on the output of device by using a high frequency oscilloscope which demonstrates the reasonability of the hypothesis.

SEFI Protection for Nanosat 16-Bit Chip Onboard Computer Memories

Plans to launch miniaturized satellite missions have been increasing in the last few years. Space missions like these are exposed to radiation, which is a cause of errors in electronic systems. Memories are one of the electronic systems that need special attention. Radiation effects in memories include single-event upsets (SEUs), multiple cell upsets, and single-event functional interrupts (SEFIs). In this paper, two solutions are presented to protect a nano/pico satellite onboard computer memory prototype with 16-bit data words against SEFIs and SEUs. The prototype uses a 32-bit memory interface, organized in two 16-bit chips. The approach to provide the error-correction capabilities is based on orthogonal latin square codes. The results show that the area and delay introduced by the solutions are acceptable. When a SEFI affects one of the chips, the solutions are able to recover the information using the remaining data.

Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes

Radiation effects cause several types of errors on memories including single event upsets (SEUs) or single event functional interrupts (SEFIs). Error correction codes (ECCs) are widely used to protect against those errors. For a number of reasons, there is a large interest in using double data rate type three (DDR-3) synchronous dynamic random-access (SDRAM) memories in space applications. Radiation testing results show that these memories will suffer both SEUs and SEFIs when used in space. Protection against a SEFI and an SEU is needed to achieve high reliability. In this paper, a method to protect 16-bit and 64-bit data word memories composed of 8-bit memory devices against a simultaneous SEFI and an SEU is presented. The scheme uses orthogonal Latin square (OLS) codes and can be activated when a SEFI occurs, using a conventional double error correction approach otherwise.