Single Event Effect Mitigation Research Articles

Voltage-Controlled Oscillator Utilizing Inverse-Mode SiGe-HBT Biasing Circuit for the Mitigation of Single-Event Effects

The advantages and the tradeoffs associated with the use of inverse-mode (IM) silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) biasing circuitry in radio-frequency (RF) voltage-controlled oscillators (VCOs) have been investigated and the performance of proposed VCOs (IM VCOs) is compared with VCOs with conventional forward-mode (FM) SiGe-HBTs (FM VCOs). Where the high-frequency performance of IM VCOs is inevitably degraded due to unfavorable device optimization unlike FM VCOs, IM VCOs provide acceptable low-GHz VCO circuit performance. In terms of single-event effects (SEEs), the IM VCOs show reduced transient peaks and duration in comparison with conventional FM VCOs. In addition, the performance of the VCOs is analyzed in terms of transient error vector magnitude (TEVM) in an RF receiver (RX) using quadrature phase-shift keying (QPSK) modulation under a radiation environment. The IM VCOs in the RX circuit show better reliability under SEEs, offering 28.2% lower TEVM at a 64 Mb/s data rate, than that of the RX circuit with conventional FM VCOs. Therefore, the application of IM SiGe-HBT biasing circuits for RF VCOs can be a viable SEE-hardening technique for space-based RF systems. The VCO prototype was fabricated using IHP 130-nm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology.

Spin-Transfer Torque Magnetic Tunnel Junction for Single-Event Effects Mitigation in IC Design

For embedded systems in harsh environments, a radiation robust circuit design is still an open challenge. As complementary–metal–oxide semiconductor (CMOS) processes get denser and smaller, their immunity toward particle strikes decreases drastically. Due to its good radiation effects tolerance and its inherent nonvolatility, spin-transfer torque magnetic tunnel junction (STT-MTJ) is considered a promising candidate for high-reliability electronics. Nevertheless, when integrated in a CMOS circuit, these magnetic devices could still be affected by upsets. To decrease the probability of this occurrence, a radiation robust setup is used to calibrate a physics-based 20-nm MTJ compact model, integrated in a 28-nm Fully Depleted Silicon On Insulator (FD-SOI) technology. Thus, a radiation hardening by design (RHBD) solution is presented, where a nonvolatile sequential block enables one to mitigate the single-event effects (SEEs).

Adaptive single-event effect mitigation for dependable processing systems based on FPGAs

For FPGA-based applications in harsh radiation environments, designers apply mitigation techniques according the worst-case (solar) condition to achieve a dependable design. This results in a resource overhead, which is most of the time unnecessary. To overcome this problem, an adaptive mitigation technique is used, which is a trade-off between two parameters, such as performance and reliability. We propose an Adaptive Single-Event Effect Mitigation (ASEEM) method, based on FPGA reconfiguration between a performance mode and a reliability mode. The performance mode offers high processing power and the reliability mode offers a high dependability. We evaluate ASEEM by calculating results using particle flux data from 2010 until 2017 for one space-grade and two commercial-grade FPGAs. Based on radiation data, we calculate upset rates, availability, performance, and performability. We optimize the performability, which is the benchmark parameter, in dependence of the Mean Time to Repair (MTTR) and time configured in the performance mode. We conclude that the performability of ideal ASEEM (without implementation losses) maximizes with an improvement of 132% over the compared static modes (performance and reliability) at an MTTR of 19.8 h and 91% of the time in the performance mode for the space-grade FPGA. ASEEM is implemented as FPGA design to determine the implementation impact.

Single Event Effects mitigation with TMRG tool

Single Event Effects (SEE) are a major concern for integrated circuits exposed to radiation. There have been several techniques proposed to protect circuits against radiation-induced upsets. Among the others, the Triple Modular Redundancy (TMR) technique is one of the most popular. The purpose of the Triple Modular Redundancy Generator (TMRG) tool is to automatize the process of triplicating digital circuits freeing the designer from introducing the TMR code manually at the implementation stage. It helps to ensure that triplicated logic is maintained through the design process. Finally, the tool streamlines the process of introducing SEE in gate level simulations for final verification.

Erratum to “Single-Event Effect Mitigation in Switched-Capacitor Comparator Designs” [Dec 08 3440-3446

Erratum to “Single-Event Effect Mitigation in Switched-Capacitor Comparator Designs” [Dec 08 3440-3446

Single-Event Effect Mitigation in Switched-Capacitor Comparator Designs

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A radiation-hardened-by-design (RHBD) technique is described for reducing errors due to single-event effects at the floating input nodes of a switched-capacitor comparator. The technique is shown to significantly outperform the alternative “brute force” design choice of increasing capacitor size. </para>