Single-ended Low-noise Amplifier Research Articles

A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET

The world’s first 5-carrier aggregation (CA) supporting digital-intermediate frequency (IF) receiver (RX) to support 5G sub-6 GHz new radio (NR) and CA/E-UTRA NR dual connectivity (CA/EN-DC) maintaining 2G and 3G in 14-nm FinFET CMOS technology is presented. Three digital-IF RXs with a shared local oscillator-phase-locked loop (LO-PLL) are integrated for supporting inter-/intra-band 5-CA to reduce power consumption and area of the massive number of RX paths. The RX features nine single-ended low-noise amplifiers (LNAs) with low/mid/high band (L/M/HB) characteristics. It achieves noise figure (NF) of 1.5 dB with 18 dB external LNA gain and +7.6-dBm out-of-band (OOB) input intercept point 3 (IIP3), and input intercept point 2 (IIP2) calibration is not required thanks to IF planning. The RX achieves an error vector magnitude (EVM) of 2.5% by intra-4CA for B1 LTE10MHz and LTE20MHz in one single RX path, as well as inter-3CA for B3, B5, and B7 long-term evolution (LTE) 20 MHz with a shared LO-PLL. The estimated power saving by sharing a single LO-PLL is 17% compared to 3-CA RXs with three separate LO-PLLs.

Design and Analysis of a 28 GHz T/R Front-End Module in 22-nm FD-SOI CMOS Technology

This article presents practical design considerations and methodologies for a 28-GHz front-end module (FEM) in 22-nm fully depleted silicon on insulator (FD-SOI) CMOS technology for the fifth generation (5G) wireless communication. The design adopts a gain-boosting technique that is comprehensively analyzed with a transformer-based stacked-FET power amplifier (PA). Then, the co-design of the transmit/receive (T/R) switch with the PA and low-noise amplifier (LNA) is investigated, and an electrostatic-discharge (ESD)-aware T/R switch incorporating PA circuitry is proposed to leverage the Tx- and Rx-mode performance. Moreover, the robustness of standalone PA and Tx-mode FEM is simulated and experimentally verified. Furthermore, the ground return paths and supply parasitic paths of the adopted single-ended LNA together with the proposed T/R switch are studied, properly simulated, and assessed. Finally, the proposed PA topology is first verified standalone, exhibiting 32-dB power gain ( G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ), an 18.2-dBm output 1-dB compression point (OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> ), and a 31.1% power-added efficiency (PAE) at OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> (PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> ). Using this PA in the FEM yields a Tx-mode OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> /PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> of 16 dBm/19.4%, and an average output power (Pout <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</sub> )/PAE of 10.1 dBm/8.3% for a 100-MHz bandwidth 256-QAM single-carrier signal at an error-vector magnitude (EVM) of -30 dB. In the Rx mode, noise figure (NF) and input-referred third-order intercept point (IIP3) are 3.2 and -5.4 dBm, respectively. A 2-kV human-body model (HBM) ESD protection of the FEM is predicted in transient simulations and measured with transmission line pulse (TLP) tests.

High-bandwidth, variable-resistance differential noise thermometry.

We have developed Johnson noise thermometry applicable to mesoscopic devices with variable source impedance with high bandwidth for fast data acquisition. By implementing differential noise measurement and two-stage impedance matching, we demonstrate noise measurement in the frequency range of 120 MHz-250MHz with a wide sample resistance range of 30 Ω-100kΩ tuned by gate voltages and temperature. We employed high-frequency, single-ended low noise amplifiers maintained at a constant cryogenic temperature in order to maintain the desired low noise temperature. We have achieved thermometer calibration with temperature precision up to 650 μK measuring a 200 mK temperature modulation on a 10K background with 30s of averaging. Using this differential noise thermometry technique, we measured thermal conductivity on a bilayer graphene sample spanning the metallic and semiconducting regimes in a wide resistance range, and we compared it to the electrical conductivity.

Power-Efficient CMOS Cellular RF Receivers for Carrier Aggregation According to RF Front-End Configuration

This article presents power-efficient radio frequency (RF) receiver designs, particularly for advanced long-term evolution cellular applications. The two proposed single-ended receiver architectures can fully support multiple-channel RF signals in advanced carrier aggregation (CA) scenarios with maximum design flexibility depending on the RF front-end module configuration and target applications. Two different low-noise amplifier (LNA) topologies are employed in receivers to achieve different bandwidth handling capabilities and linearity requirements. The first receiver architecture utilizes narrowband LNAs with a current-reusing technique using a 28-nm low-power complementary metal-oxide-semiconductor (CMOS) technology. The proposed receiver with this single-ended narrowband LNA can handle up to three carrier components (CCs) CA. The second receiver architecture shows wideband characteristics and employs current-efficient and high linear wideband LNAs. This proposed design can support up to five CC CA and is implemented in a 14-nm Fin field-effect-transistor CMOS technology. Moreover, frequency-band switchable transformers are utilized in both designs to realize size-efficient receivers. Both proposed receivers operate at a frequency ranging from 0.6 to 2.7 GHz. The implemented narrowband and wideband receivers have conversion gains exceeding 70 and 62 dB, and achieve noise figures of less than 3.5 and 5 dB during all CA scenarios, respectively. The proposed receivers operate at a nominal supply of 1.2 and 1.0 V for 28 and 14-nm CMOS technologies, respectively.

A Package Aware QLMVF Receiver Front End

This brief presents a 2.4 GHz receiver front end in the form of architecture of quadrature LNA-Mixer-VCO-filter (QLMVF) cell in 180 nm CMOS with split-transconductance amplifiers (TCAs). Instead of a single stack-current-reusing QLMV scheme, the proposed design employs two separate current reuse stages with a passive mixer to provide better flicker noise and linearity performance. A shunt-inductive input-match single-ended low noise amplifier (LNA) proposed with an improved package parasitic compensation through a simple varactor tuning. The quad-flat-no-leads (QFN) packaged receiver provides a measured maximum conversion gain of 40 dB, a noise figure (NF) of 10 dB, and a third-order input intercept point (IIP3) of -5 dBm with a spurious-free dynamic range (SFDR) of 60 dB. The front end consuming 2.7 mW of power from a 1.8 V supply and occupies an area of 1.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS

The world’s first single-chip RF transceiver to support 5G sub-6-GHz new radio (NR) and long-term evolution (LTE) E-UTRA New Radio-Dual Connectivity (EN-DC) in 14-nm FinFET CMOS technology is presented. The single-chip transceiver integrates identical primary and diversity receivers (RXs) with seven pipelines for supporting four inter-band carrier aggregation (CA) with three 4 $\times $ 4 MIMO, two independent transmitter (TX) chains, eight frequency synthesizers for RX and TX, and on-chip digitally controlled crystal oscillator (DCXO) to reduce the phase noise and bill of material (BOM) cost. The receiver features 12 single-ended low-noise amplifiers (LNAs) with wideband characteristics. With the help of the proposed pipeline structure and frequency-band switchable transformer, the die size can be reduced despite covering the whole frequency range from 2G to sub-6-GHz 5G NR. It achieves the noise figure (NF) from 6.5 to 9.3 dB, +3-dBm out-of-band (OOB) IIP3, more than +70-dBm OOB IIP2 after calibration. For the transmitter, low RX-band noise and harmonic suppression technique are applied to support surface acoustic wave (SAW)-less architecture, and the bandwidth control of the baseband filter is implemented for the digital pre-distortion (DPD) operation of 100-MHz BW in NR transmit data. The measured error vector magnitudes (EVMs) in 4G and 5G bands of n79 are −39.5 dB at +4-dBm output power and −33.9 dB at +3.06-dBm output power, respectively, and the measured RX-band noise of 2G is −163 dBc at 20-MHz offset. The RX consumes 18 mW at LTE 1-CA mode and the TX consumes 350 mW at n79.

A 65-nm CMOS &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$2\times2$ &lt;/tex-math&gt; &lt;/inline-formula&gt; MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations

This paper presents a 680 MHz–6 GHz $2 \times 2$ multiple-input and multiple-output (MIMO) long-term evolution (LTE) RF transceiver in 65-nm CMOS for low-cost and multi-band capable femtocell base stations. The transceiver integrates two receivers (RXs), two transmitters (TXs), and two frequency synthesizers, for the $2 \times 2$ MIMO operation to support both the frequency division duplex (FDD) and the time division duplex (TDD) modes. Each pair of an RX and a TX features eight single-ended low noise amplifiers (LNAs), and eight TX outputs that extensively share active and passive circuits with minimal performance degradation. In the measurement, each RX illustrates the noise figure (NF) from 2.9 to 5.2 dB, the input-referred third-order intercept point (IIP3) of more than −2 dBm, and the IIP2 of more than 48 dBm, over the entire frequency range at the maximum gain. Each TX achieved the adjacent channel leakage ratio (ACLR) that was less than −54 dBc at −5-dBm output power with −157-dBc/Hz phase noise at the RX band, while achieving an error-vector-magnitude (EVM) of less than 2.8%, over the entire frequency range. The transceiver, packaged in a flip-chip chip-scale package (fcCSP), is mounted on the board of the commercial femtocell of the LTE Band5, along with a commercial duplexer, power amplifier, and modem. The femtocell achieved −100-dBm reference sensitivity without the use of an external LNA. It also achieved −51-dBc TX ACLR and 1.68% TX EVM at 20-dBm output power in the LTE 10-MHz mode with the $2 \times 2$ MIMO configuration, without applying a digital pre-distortion (DPD) technique.

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed. A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA. The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies. Implemented in a 0.18 [Formula: see text]m CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 16.4 dB across the 3 dB bandwidth of 0.2–3 GHz. The in-band noise figure of 3.4–4.7 dB is obtained while the IIP3 of 5.3–6.8 dBm and IIP2 of 12.5–17.2 dBm are post-simulated in the designed frequency band. The LNA core consumes a power dissipation of 3.8 mW under a 1.5 V power supply.

A Low Cost Bluetooth Low Energy Transceiver for Wireless Sensor Network Applications with a Front-end Receiver-Matching Network-Reusing Power Amplifier Load Inductor.

In this work, a low cost Bluetooth Low Energy (BLE) transceiver for wireless sensor network (WSN) applications, with a receiver (RX) matching network reusing power amplifier (PA) load inductor, is presented. In order to decrease the die area, only two inductors were used in this work. Besides the one used in the voltage control oscillator (VCO), the PA load inductor was reused as the RX impedance matching component in the front-end. Proper controls have been applied to achieve high transmitter (TX) input impedance when the transceiver is in the receiving mode, and vice versa. This allows the TRX-switch/matching network integration without significant performance degradation. The RX adopted a low-IF structure and integrated a single-ended low noise amplifier (LNA), a current bleeding mixer, a 4th complex filter and a delta-sigma continuous time (CT) analog-to-digital converter (ADC). The TX employed a two-point PLL-based architecture with a non-linear PA. The RX achieved a sensitivity of −93 dBm and consumes 9.7 mW, while the TX achieved a 2.97% error vector magnitude (EVM) with 9.4 mW at 0 dBm output power. This design was fabricated in a 0.11 μm complementary metal oxide semiconductor (CMOS) technology and the front-end circuit only occupies 0.24 mm2. The measurement results verify the effectiveness and applicability of the proposed BLE transceiver for WSN applications.

A Transformer Feedback &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${G}_{m}$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Boosting Technique for Gain Improvement and Noise Reduction in mm-Wave Cascode LNAs

This paper presents the analysis and design of a novel topology of a low-noise amplifier (LNA) with gain improvement and noise reduction simultaneously. A transformer feedback ${ g}_{ m}$ -boosting technique is proposed in a single-ended cascode topology to increase the gain and reduce the noise. The proposed technique is theoretically formulated and detailed analyses are presented. Two V-band single-ended cascode LNAs, with a transformer and transmission line for impedance matching, respectively, are demonstrated to verify this technique. Fabricated in a 65-nm CMOS process, the transformer-based (TF-based) LNA exhibits a minimum noise figure (NF) of 3.6 dB at 53.5 GHz and a highest power gain of 28.2 dB at 54 GHz in measurement. To our best knowledge, this LNA has the best NF and power gain among all the published V-band LNAs in 65-nm CMOS up to date. The transmission-line-based (TL-based) LNA exhibits a minimum NF of 3.8 dB at 53.9 GHz and a highest power gain of 25.4 dB at 54.2 GHz in measurement. Both the LNAs consume 18 mA from a power supply of 1.1 V.

Low-Loss Integrated Passive CMOS Electrical Balance Duplexers With Single-Ended LNA

A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky surface acoustic wave (SAW) and bulk acoustic wave (BAW) duplexers in third-generation (3G)/fourth-generation (4G) cellular transceivers. A balancing network creates a replica of the transmitter (TX) signal for cancellation at the input of a single-ended low-noise amplifier (LNA) to isolate the receive path from the TX. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra baluns at the antenna side. The balancing network enables a single-ended LNA with reliable high TX power operation up to 22 dBm by alleviating the common-mode coupling. The duplexer achieves around 50-dB transmitter-receiver (TX-RX) isolation within a 1.6-2.2-GHz range. The cascaded noise figure (NF) of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in a 0.18-μm CMOS process and occupy an active area of 0.35 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Multi‐mode noise parameters for multi‐port networks

This study derives an equation set by which the equivalent multi-mode noise parameters of a general multi-port receiver can be solved in terms of the noise parameters of the constituent single-ended (SE) low-noise amplifiers (LNAs). The expressions are used to derive equivalent differential- and common-mode noise parameters for a pair of balanced LNAs as well as the equivalent multi-mode noise parameters of four SE LNAs excited through a quadraxial transmission line.

Toward Realization of 2.4 GHz Balunless Narrowband Receiver Front-End for Short Range Wireless Applications.

The demand for radio frequency (RF) transceivers operating at 2.4 GHz band has attracted considerable research interest due to the advancement in short range wireless technologies. The performance of RF transceivers depends heavily on the transmitter and receiver front-ends. The receiver front-end is comprised of a low-noise amplifier (LNA) and a downconversion mixer. There are very few designs that focus on connecting the single-ended output LNA to a double-balanced mixer without the use of on-chip transformer, also known as a balun. The objective of designing such a receiver front-end is to achieve high integration and low power consumption. To meet these requirements, we present the design of fully-integrated 2.4 GHz receiver front-end, consisting of a narrow-band LNA and a double balanced mixer without using a balun. Here, the single-ended RF output signal of the LNA is translated into differential signal using an NMOS-PMOS (n-channel metal-oxide-semiconductor, p-channel metal-oxide-semiconductor) transistor differential pair instead of the conventional NMOS-NMOS transistor configuration, for the RF amplification stage of the double-balanced mixer. The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz. The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area. Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN).

Design of a full-band CMOS UWB receiver and fast-hopping carrier generator for 3.1–10.6 GHz

This paper presents an interference rejection full-band UWB receiver and fast hopping carrier generator for 3.1---10.6 GHz. This receiver enables 11 bands of operation by embedding a tunable notch filter to eliminate interferers in a 5 GHz wireless local area network. The carrier generator can cover 3.1---10.6 GHz within less than 9.5 ns. The receiver, based on the proposed multi-band OFDM standard, consists of a zero-IF receive chain and required system noise figure, the receiver linearity specifications of which are discussed in this paper. It consists of a single-ended low-noise amplifier (LNA), a down-conversion mixer, a low-pass filter (LPF), and a programmable gain amplifier with an IO buffer. The LNA employs a common-gate topology of the 1st stage with dual-resonant loads, a cascade amplifier of the 2nd stage for mid-band resonance, and a tunable notch filter. The down-conversion mixer adopts a single-balanced architecture with LO cancellation. The LPF is implemented based on an active RC topology, and implements a four-stage programmable gain amplifier. The receiver dissipates 49.3 mA from a 1.8 V power supply. The average voltage conversion gain of the receiver IC is 73.5 dB, and the system noise figure is 8.4 dB. Input P1dB increases from ?36.8 dBm at 4 GHz to ?30.5 dBm at 10.3 GHz. The attenuation is 8.5 dB, which is achieved in the interference rejection band at 5.2 GHz. It occupies an area of 0.98 × 3.3 mm2 including the bond pads.

SAW-Less Analog Front-End Receivers for TDD and FDD

In cellular receivers, out-of-band blockers are generally managed by surface-acoustic-wave (SAW) filters between the antenna and the low-noise amplifier (LNA). For Time Division Duplexing (TDD), such as GSM, the SAW can be removed if the receiver can handle very large interferers (e.g. in GSM 0dBm 20 MHz away) [1]. Generally SAW filters also perform differential to single-ended (SE) conversion (balun). Once the SAW is removed an SE transceiver eliminates the external balun, reducing cost and attenuation. For the same sensitivity, a SAW-less SE transceiver can have a noise figure (NF) 2 to 3dB higher than a classical one. An SE LNA could be susceptable to couplings from supply and substrate, which are usually rejected through symmetry. Therefore it should become symmetric as closely as possible to the input pin. A SAW-less differential transceiver [2] can also be appealing if it has an NF close to that of classical transceivers. This is because it can have better sensitivity in TDD (a balun attenuates less than a SAW) and it can be very flexible, being usable for both FDD (where duplexers are differential) and TDD.

Low noise amplifier for radio astronomy

A compact, microstrip, two-stage, room temperature, single-ended low noise amplifier (LNA) is designed using commercial components for Aperture Tile in Focus (APERTIF), a square kilometre array (SKA) pathfinder project. Various techniques are investigated to insert inductance between the source pad of the package and the ground plane of the printed circuit board (PCB), with the chosen design able to do this using standard manufacturing techniques. The desired noise temperature of 25 K (noise figure (NF) of 0.36 dB) is met over the 1.0–1.8 GHz band, with an input return loss better than 10 dB.

245-GHz LNA, Mixer, and Subharmonic Receiver in SiGe Technology

A four-stage common-base (CB) 245-GHz low-noise amplifier (LNA) and a fourth subharmonic 245-GHz transconductance mixer are presented. An integrated subharmonic receiver for sensing applications in the 245-GHz industrial-scientific-medical band is proposed. The receiver consists of a single-ended CB LNA, a fourth transconductance subharmonic mixer, a 60-GHz push-push voltage-controlled oscillator with a 1/32 divider, and an IF amplifier. It is fabricated in an SiGe: C BiCMOS technology with f T and fmax of 300 and 500 GHz, respectively. Its measured single-ended gain is 21 dB at 243 GHz with a tuning range of 12 GHz, and a noise figure of 33 dB. The input 1-dB compression point is -37 dBm . The receiver dissipates at 358 mW.

52–75 GHz wideband low-noise amplifier in 90 nm CMOS technology

A three-stage single-ended low-noise amplifier covering almost the entire V-band is presented. The design employs three cascade single-ended stages with pi-sections for wideband interstage matching and source degeneration at the first stage. The amplifier achieves a peak gain of 14 dB and minimum noise figure of 4.8 dB. A record 3 dB bandwidth of 37 is achieved with power consumption of 32 mW and core silicon area of 0.065 mm 2 in 90 nm CMOS technology.

Noise figure measurement of three-port differential low-noise amplifiers

A measurement procedure to de-embed the noise figure (NF) of a three-port differential low-noise amplifier (LNA) from single-ended (SE) measurements is presented. An approximate solution for the differential NF is found in terms of two SE noise figure and gain measurements and the sensitivity of the de-embedded NF to unsymmetrical performance is analysed. The theory presented is applied to a three-port differential LNA and the de-embedded NF is compared to that of an equivalent SE LNA design.

A Subharmonic Receiver in SiGe Technology for 122$~$GHz Sensor Applications

The iterative design of an integrated subharmonic receiver for 120-127 GHz is presented. The receiver consists of a single-ended low-noise amplifier (LNA), a push-push voltage-controlled oscillator (VCO) with 1/32 divider, a polyphase filter, and a subharmonic mixer. The receiver is fabricated in SiGe:C BiCMOS technology with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 255 GHz/315 GHz. In the first design the differential down-conversion gain of the receiver is 25 dB at 127 GHz, and the corresponding noise figure (NF) is 11 dB. The 3 dB bandwidth reaches from 125 GHz to 129 GHz. The input 1 dB compression point is at - 40 dBm. The receiver draws 139 mA from a supply voltage of 3.3 V. A subsequent design demonstrates 31 dB differential gain at 122 GHz, and 11 dB NF. The 3 dB bandwidth is from 121 GHz to 124 GHz. The receiver has a NF of 8 dB for 3 GHz IF frequency due to integrated RF bandpass-filtering. It is realized by the lower NF of the LNA, and the LNA itself.