Single-ended Structure Research Articles

Single-sided gate-wrap-around CNTFET SRAM cell for utilization in reliable IoT-based platforms

This paper proposes a novel design of an 11-transistor SRAM bit-cell with a single-ended structure and memory mini-array with the bit-interleaving architecture support using the gate-diffusion input (GDI) method based on the gate-wrap-around (GWA) CNTFETs technology. The cell core of the suggested design is composed of a robust cross-coupled structure of two asymmetric inverters based on circuit-level methodologies. The proposed bit-cell scheme exhibits significant features such as improved write-ability, read data stability, and reduced leakage/short-circuit power due to the asymmetric write-assist method and inverter gates with stacked transistors, respectively. The simulation analysis has been done based on criteria such as static noise margins (SNMs), power-delay product (PDP), and the electrical quality/yield-based figure of merits (FoMs) in write/hold/read operation cycles. The suggested SRAM bit-cell demonstrates the best results with an average of 9.36 %, 48.53 %, and 22.82 %, respectively, for FoMs against other SRAM bit-cell schemes. The Monte-Carlo simulations in the 16-nm node show better results for the proposed bit-cell in the energy and failure probability per operation cycles than similar designs, with the best performance on average of 27 % and 8 %, respectively.Finally, to investigate the effectiveness of the suggested memory cell in the real application domain, an on-chip scaled power supply memory architecture for storing digital data based on quick response (QR) code using the proposed hardware algorithm is evaluated. Our results certify that the suggested memory array configuration in comprehensive FoMs based on quality and hardware efficiency metrics shows better results than the counterpart memory architecture.

Reliability and Characteristic Analysis Considering the Circuit Structure and Operation Risk of Forward Converters

The forward converter is divided into two circuit topologies depending on the method of resetting the energy stored in the magnetizing inductance of the transformer: a single-ended structure using a reset circuit and a double-ended structure called a two-switch forward converter and, accordingly, a difference occurs in the operational mode. Generally, forward converters are designed with low power of less than 500 W and are sold at low prices, so it is common to replace them in case of failure. However, in terms of environmental conservation through resource saving, it is desirable to design with as high reliability as possible. In this paper, reliability is analyzed for the two representative circuit topologies of forward converters. The conventional PCA (part count failure analysis) method determines the failure rate only by the number of circuit components constituting the converter and the correlation between the components, but the FTA (fault-tree analysis) method can additionally consider the operation risk of the converter according to the circuit configuration and operation. Therefore, it is possible to analyze the failure rate according to the operating characteristics of the two converters from the difference in the failure rate obtained by the two methods. In addition, the two converters were manufactured as a 300 W prototype, respectively, and the volume, weight, and power loss were compared, and the economic feasibility was analyzed based on the cost model.

A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave. It adopts a three-stage single-ended structure at 28GHz. An analog predistortion linearization method is used to improve the linearity of the power amplifier (PA). As a result, there is a significant improvement in power-added efficiency (PAE) and linearity is achieved. The Ka-band PA is implemented in TSMC 65nm CMOS process. At 1.2V supply voltage, the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%. After linearization, the output power at the 1dB compression point is increased by 2dBm, with efficient gain compensation performance.

Balanced to Unbalanced: An Overview of Multifunctional Wideband Balanced-to-Unbalanced Four- and Five-Port Filtering Power Dividers

Fifth-generation (5G) communication techniques are growing in popularity, and 5G will become the commercial operation standard for mainland China in 2020 [1]. As the next-generation mobile communication network, 5G will not only greatly improve communication efficiency; it will also change the way people live and work. The 5G communication system contains the millimeter-wave and sub-6-GHz bands. For the sub-6-GHz band, circuits are becoming ever more compact and multifunction; thus, electromagnetic interference and multicoupling problems will greatly affect the entire system's performance [2]-[4]. In response, balanced circuits with higher immunity to environmental noises [5]-[8], lower electromagnetic interference [9]-[11], and better dynamic range [12]-[15] have attracted increasing attention in the past few years, and a large number of balanced circuits are being conceived [16], [17]. Currently, all feature differential-mode input and output terminals, so they cannot be connected directly to single-ended circuits. Balanced filters, antennas, and power dividers that can be cointegrated with balanced active circuits are required for the development of fully balanced transmitter and receiver RF chains, such as the balanced power dividers that can be connected to a Doherty power amplifier in a balanced system. In this case, balancing is only necessary at the input and output stages. It is expected that the transistor stage is still a single-ended structure, where only two amplifier devices are needed [18].

Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping

This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally flipped during write operations to reach the more beneficial state for storage. A 1-kb SRAM block of low-voltage memory cells was implemented and manufactured in a 130-nm CMOS. The memory cells were made writable and read-stable at low supply voltages with a single-ended write and single-ended read structure using six multithreshold transistors that give rise to an asymmetric retention power. At a supply voltage of 350 mV, the content-dependent leakage power in the asymmetric memory cell is 23 times smaller when storing logic “1”s compared with logic “0”s. A derived statistical model suggests that the mean, wordwise, static power savings of the word-flipping scheme become 15.70% for 8-bit words of uniform bit probability. For the implemented SRAM macro, the mean improvement for the retention power is, including flip logic and decoder and driver overheads, found to be 14.69%. In boundary tests, by writing all words full of undesired values, the power saving becomes 80.37%, while writing all words full of desired values causes a power penalty of 6.14%. Measurement results confirm the improvement in retention power with a ten-chip mean improvement of 11.93% for the same data set.

A Quantized Analog RF Front End

A surface acoustic wave (SAW)-less receiver with a quantized analog RF front end is presented. The front end is composed of 100 smaller unit front ends, each one dedicated to process only a portion of the input signal. This allows the compression point of the structure to be increased beyond the voltage supply and to reconfigure the dynamic range to fit different operative conditions. A prototype integrated in 65-nm CMOS is presented, where the 1-dB compression point can go up to 10.5 dBm under 0.8-V supply, while the noise figure can be lowered down to 1.5 dB. The RF front end and the baseband burn 14 mW, while clock generation and distribution burn 37.2 mW/GHz. Upon the configuration, IIP3 varies between 1 and 20.5 dBm, while IIP2 between 35 and 75 dBm with a single-ended structure. The third- and fifth-order harmonic rejections are over 40 and 47 dB, respectively. The active area is only 0.25 mm2.

Linearity improvement of differential CMOS low noise amplifier

<p>This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S<sub>21</sub> gain of 18.56 dB, noise figure (NF) of 1.85 dB, S<sub>11</sub> of −27.63 dB, S<sub>22</sub> of -34.33 dB, S<sub>12</sub> of −37.09 dB and IIP3 of -7.79 dBm.</p>

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed. A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA. The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies. Implemented in a 0.18 [Formula: see text]m CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 16.4 dB across the 3 dB bandwidth of 0.2–3 GHz. The in-band noise figure of 3.4–4.7 dB is obtained while the IIP3 of 5.3–6.8 dBm and IIP2 of 12.5–17.2 dBm are post-simulated in the designed frequency band. The LNA core consumes a power dissipation of 3.8 mW under a 1.5 V power supply.

The Birth and Demise of the ISApl1-mcr-1-ISApl1 Composite Transposon: the Vehicle for Transferable Colistin Resistance.

ABSTRACTThe origin and mobilization of the ~2,609-bp DNA segment containing the mobile colistin resistance gene mcr-1 continue to be sources of uncertainty, but recent evidence suggests that the gene originated in Moraxella species. Moreover mcr-1 can be mobilized as an ISApl1-flanked composite transposon (Tn6330), but many sequences have been identified without ISApl1 or with just a single copy (single ended). To further clarify the origins and mobilization of mcr-1, we employed the Geneious R8 software suite to comprehensively analyze the genetic environment of every complete mcr-1 structure deposited in GenBank as of this writing (September 2017) both with and without associated ISApl1 (n = 273). This revealed that the 2,609-bp mcr-1 structure was likely mobilized from a close relative of a novel species of Moraxella containing a chromosomal region sharing >96% nucleotide identity with the canonical sequence. This chromosomal region is bounded by AT and CG dinucleotides, which have been described on the inside ends (IE) of all intact Tn6330 described to date and represent the ancestral 2-bp target site duplications (TSDs) generated by ISApl1 transposition. We further demonstrate that all mcr-1 structures with just one ISApl1 copy or with no ISApl1 copies were formed by deletion of ISApl1 from the ancestral Tn6330, likely by a process related to the “copy-out–paste-in” transposition mechanism. Finally, we show that only the rare examples of single-ended structures that have retained a portion of the excised downstream ISApl1 including the entire inverted right repeat might be capable of mobilization.

An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network. The input range is twice the reference voltage. The ADC’s loading of the previous stage is reduced by using a single-ended structure, and by eliminating the largest capacitor in the array. The common mode voltage of the input signal can be used as reference voltage. All building blocks were designed in subthreshold for power efficiency, with an asynchronous self-controlled SAR logic. The ADC was fabricated in 0.18 – $\mu \text{m}$ CMOS 2P4M process. The measured peak SNDR was 60.5 dB, the SFDR was 72 dB, the DNL +0.6/−0.37 LSB, and the INL +0.94/−0.89 LSB. The total power consumption was 250 nW from 0.75-V supply voltage.

$V$ -band $\times 8$ Frequency Multiplier With Optimized Structure and High Spectral Purity Using 65-nm CMOS Process

This paper proposes a V-band $\times 8$ frequency multiplier for 60-GHz wireless communication systems using 65-nm CMOS technology. The $\times 8$ frequency multiplier consists of three stages of amplifiers and three stages of doublers. The second and fifth stages of the frequency multiplier are balanced structures, while the third stage of the frequency multiplier is a single-ended structure. The proposed $\times 8$ frequency multiplier is optimized, and it has low power consumption, high spectral purity, and a small size. It occupies an area of $1.32 \times 0.7$ mm2 and achieves a maximum output power of −1.8 dBm with an input power of −24 dBm in the frequency range of 46.4–52 GHz. The circuit consumes 55 mA from a 1-V supply. All harmonic suppressions are over 37.6 dBc in the frequency range of 46.4–52 GHz. These results represent the state-of-the-art for CMOS frequency multipliers.

Differential Second-Order Voltage-Mode All-Pass Filter Using Current Conveyors

In this paper, a new circuit solution of analogue pseudo-differential second-order all-pass filter operating in the voltage mode is presented. Pseudo-differential, since both input and output terminals are differential, however, the circuit topology features single-ended structure. As active elements the differential difference current conveyors and second-generation current conveyors are advantageously used. The proposed filter features quality factor control without disturbing the pole-frequency using single passive element. The designed circuit is less complex compared to fully-differential solutions by maintaining sufficient common-mode rejection ratio. The behaviour of the filter is described by means of symbolic analysis and also by simulations using the UCC-N1B integrated circuit. Furthermore, the performance of the proposed pseudo-differential filter has been validated by experimental measurements.DOI: http://dx.doi.org/10.5755/j01.eie.22.5.16344

60 GHz CMOS gain‐boosted LNA with transformer feedbacked neutraliser

A 60 GHz low-noise amplifier (LNA) using standard 65 nm CMOS technology is presented. A gain of the 60 GHz amplifier was boosted by using a transformer feedbacked capacitor neutraliser. To stabilise the process variations caused by the positive feedback system, the body node of the triple well was adjusted to tune the capacitor value. The theory, simulation and measurements are presented. An implementation prototype is evaluated using on-wafer proving. The LNA showed a measured peak gain of 30 dB and a measured noise of 4.6 dB under 8.9 mW power consumption with a 1 V supply voltage. The measured IIP3 was −26 dBm. This is believed to be the first CMOS 60 GHz LNA to compensate the overlap capacitor with a single-ended structure.

A monolithic 60 GHz balanced low noise amplifier**Project supported by the External Cooperation Program of BIC, Chinese Academy of Sciences (No. 172511KYSB20130108).

This paper presents a 60 GHz balanced low noise amplifier. Compared with single-ended structures, the balanced structure can obtain a better input/output return loss, a lower noise figure (NF), a 3 dB improvement of the 1 dB compression point, a 6 dB improvement of IM3 and a doubled dynamic range. Each single-ended amplifier in this paper uses a four-stage cascade structure to achieve a high gain in broadband. At the operating frequency range of 59–64 GHz, the small signal gain of the balanced amplifier is more than 20 dB. Both the input and output return losses are less than −12 dB. The output 1 dB compression power is 10.5 dBm at 60 GHz. The simulation result for the NF is better than 3.9 dB. The chip is fabricated using a 0.15 μm GaAs pHEMT process with a size of 2.25 × 1.7 mm2.

AN ultra-wideband SiGe BiCMOS LNA for W-band applications

This article presents the design steps and implementation of a W-band ultra-wideband low noise amplifier (LNA) for both automotive and imaging applications. Three amplifiers based on common-emitter topology with different configurations are manufactured using IHP 0.13 mu m SiGe BiCMOS 300/500 GHz (f(t)/f(max)) SG13G2 technology. A three-stage single-ended structure is proposed for ultra-wideband imaging purposes. As the results are analyzed, this 0.2 mm(2) LNA can operate in a 25 GHz of measured 3-dB bandwidth in W-band with 21 dB peak gain and 4.9 dB average noise figure using 1.5 V supply voltage. It consumes 50 mW of power in the edge operation conditions and the output 1 dB compression point is found as -4 dBm. To the authors' knowledge, this chip achieves one of the best overall performances compared to other W-band LNAs.

Strain variation measurement with short‐time Fourier transform‐based Brillouin optical time‐domain reflectometry sensing system

A novel technique to perform dynamic strain measurement with a Brillouin optical time-domain reflectometry (BOTDR) sensing system based on short-time Fourier transform (STFT) is proposed. Unlike traditional frequency scanning methods, the proposed system samples the Brillouin backscattering signal directly after it has been downconverted to the intermediated frequency (IF) region. The Brillouin frequency shift (BFS) of the sensing fibre was reconstructed from the recorded time-domain data continuously without dead-time, which provided a much higher refreshing rate of the strain measurement. Therefore, dynamic strain variation over an optical fibre can be measured with a single-end structure that is more flexible and reliable. A 16.7 Hz strain variation on a 12 m section was successfully detected at the end of a 270 m sensing fibre with 4 m spatial resolution and 45 μe uncertainty.

A 5GHz Analog Laser Diode Driver for Radio-over-Fiber Transmission Applications

The design of an analog laser diode (LD) driver for 5GHz radio-over-fiber (ROF) transmission systems is presented in this paper. The proposed linear LD driver adopted a single-ended two-stage amplifier structure with the operating voltages of 1.8V and 3.3V respectively. The technique of self-biased cascade amplifier is employed to increase the gain and alleviate the danger of gate oxide breakdown. The simulation results show that the analog amplifier achieves the power gain of 35dB and the output 1dB compression point of 18dBm at 5GHz. The corresponding output modulation current is up to 50mA at the 1dB compression point. The total chip area is only 710μm×580μm with the all on chip input and output matching network, and the power consumption is 130mW.

Ultralow-phase-noise oscillators based on BAW resonators

This paper presents two 2.1-GHz low-phase noise oscillators based on BAW resonators. Both a single-ended common base structure and a differential Colpitts structure have been implemented in a 0.25-μm BiCMOS process. The detailed design methods including the realization, optimization, and test are reported. The differential Colpitts structure exhibits a phase noise 6.5 dB lower than the single-ended structure because of its good performance of power noise immunity. Comparison between the two structures is also carried out. The differential Colpitts structure shows a phase noise level of -87 dBc/Hz at 1-kHz offset frequency and a phase noise floor of -162 dBc/Hz, with an output power close to -6.5 dBm and a core consumption of 21.6 mW. Furthermore, with the proposed optimization methods, both proposed devices have achieved promising phase noise performance compared with state-of-the-art oscillators described in the literature. Finally, we briefly present the application of the proposed BAW oscillator to a micro-atomic clock.

A Flyback Switching Power Supply Based on L6561 for LED

A flyback switching power supply was designed, which can drive LED stability. The switching power supply is the single-ended flyback structure, and based on PWM driver chip L6561. The input voltage range of the switching power supply is 85V to 265V. The output voltage is 15V and the maximum output current is 2A. The switch power supply is suitable for mobile phone, office equipment and LED. According to experiment, the switching power supply can steadily drive 5 LED, the ripple factor of output is 1.33%, the power efficiency is 85.7%.

A Feed-Forward Power-Supply Noise Cancellation Technique for Single-Ended Class-D Audio Amplifiers

This paper presents a feed-forward power-supply noise cancellation technique to achieve high power-supply rejection ratio (PSRR) in single-ended class-D audio amplifiers. To show the effectiveness of the technique, it is implemented on a first-order single-ended pulse-width modulation (PWM) class-D amplifier. The implemented technique improves the PSRR from 20 Hz to 20 kHz independently of the close-loop compensator's filter-order. The design methodology, implementation, and tradeoffs for the proposed technique are provided. The fabricated class-D audio amplifier achieves a PSRR of 83 dB at 217 Hz, THD+N of 0.0149%, and a maximum efficiency of 94.6% from a 1.8-V power supply. Experimental results show a PSRR improvement of 33 dB from 20 Hz to 20 kHz compared to a similar amplifier designed without the technique. The prototype was implemented using 0.18- μm CMOS standard technology, and occupies a total area of 0.121 mm2. The total quiescent power consumption was 356 μW. The feed-forward power-supply noise cancellation technique enhances single-ended structures to achieve a PSRR performance comparable to differential architecture, and at the same time it consumes small quiescent power with a reduced active silicon area overhead.