Single Electron Tunneling Circuits Research Articles

Design and simulation of novel TLG–SET based configurable logic cells

Single electron tunneling circuits seem to be promising candidates as basic circuit elements of the next generation ultra-dense VLSI and ULSI circuits for their ultra-low power consumption, ultra-small size, and rich functionality. In this paper, design and simulation of novel configurable logic cells (CLCs) using single electron tunneling (SET) technology based threshold logic gate (TLG) are presented. The proposed CLC can realize all Boolean logic functions by configuring the control bits without changing the structure of the circuit and the parameters of TLG–SET based design. The logic operation of the circuit is simulated using Monte Carlo simulation. According to the simulation results, the circuit operation based on the transfer of single electrons between adjacent islands is stable.

Shot Noise in Single-Electron Tunneling Systems: A Semiclassical Model

In this paper, shot noise in single-electron tunneling circuits is studied using a semiclassical approach based on the master equation formalism where the transport through the circuit is modeled as sets of sequential stationary Poisson processes. Analytical expressions for the distribution of time between tunnel events and the resulting power spectral density S(f) are derived. The model is then used to investigate the correlated transfer of electrons and fluctuations in homogeneous long arrays of tunnel junctions.

Design analysis of metallic single electron tunneling circuits

Abstract We carried out a design study of single electron devices based on submicron metallic islands and tunnel junctions. The results of a first capacitive design analysis using a three-dimensional numerical field computation of separated circuit cells are used as input for an optimization with respect to cross-talk between neighboring circuit cells. We discuss the reduction of parasitic effects by use of additional shielding electrodes on the top of the substrate or in the background. In view of the influenced charge associated with parasitic background charges we discuss the charge distribution on a three-dimensional scan of the substrate below the structures for the study of critical influence regions, where a certain threshold of influenced charge at neighbor electrodes is given. We show that the influence calculation of the parasitic background charge is of significant importance for the design and fabrication of single charge circuits.