Single Electron Trapping Research Articles

Impact of Trap Position on Random Telegraph Noise in a 70-Å Nanowire Field-Effect Transistor

A 70-A nanowire field-effect transistor (FET) for sub-10-nm CMOS technology is designed and simulated in order to investigate the impact of an oxide trap on random telegraph noise (RTN) in the device. It is observed that the drain current fluctuation (ΔI D /I D ) increases up to a maximum of 78 % due to the single electron trapping. In addition, the effect of various trap positions on the RTN in the nanowire FET is thoroughly analyzed at various drain and gate voltages. As the drain voltage increases, the peak point for the ΔI D /I D shifts toward the source side. The distortion in the electron carrier density and the conduction band energy when the trap is filled with an electron at various positions in the device supports these results.

Low-frequency noise investigation of n-channel 3D devices

In this paper, the low-frequency (LF) noise in standard n-channel triple-gate Bulk FinFETs has been experimentally investigated with variation in the fin widths (WFin), channel lengths (L) and gate dielectric. The origin of the noise will be analyzed in order to understand the physical mechanisms involved in 3D device architectures. Although the device scaling brings the idea of noise reduction, we show the opposite behavior because already single electron trapping has a marked impact on the device operation. Significant variation in the noise spectral density has been observed, which is related to the random occurrence of excess Lorentzian components (1/f2-like), associated with generation–recombination (GR) noise. In addition, the gate-voltage-dependent GR noise peaks have been studied, which are assigned to gate oxide traps.

Single-electron injections in fringing-field-induced charge-trapping memories

In this study, single-electron and multielectron injections and trapping events on gate-to-drain non-overlapped-implantation (NOI) MOSFETs at room temperature are investigated. The trapped charges cause a reduction in the channel current through the fringing capacitance of the NOI are calculated to verify the charge numbers under various gate voltages (Vg) and drain voltages (Vd). The single-electron injection for different vertical and lateral electric fields and its probability trace are also examined by employing the lucky-electron model. These results show that single-electron injecting events play prominent roles in most of experiments under low bias conditions in the NOI MOSFETs. The significant drain current shift under single-electron injection demonstrates the NOI devices for potential single-electron storage applications.

RTN assessment of traps in polysilicon cylindrical vertical FETs for NVM application

Random telegraph noise and low-frequency noise in polysilicon device.The impact of electron trapping and detrapping events in scaled non-volatile memories.Behavior of gate oxide, interface and polysilicon traps in n-type polysilicon cylindrical vertical transistors. In this work the drain current random telegraph noise (RTN) in polysilicon-channel cylindrical vertical FET structures is studied experimentally. We show that single electron trapping events can induce significant drain current fluctuations during read operation in deeply scaled non-volatile memories (NVMs). Low-frequency (LF) noise and capture and emission time constants of the traps are also analyzed at different gate and drain bias conditions. Two independent types of traps are identified in this study, which we categorize as slow and fast states. In this paper, we show that the RTN most likely originates from traps in the highly defective channel region, in addition to the fluctuations caused by defects in the oxide close to the interface with the channel.

Trapped charge dynamics in InAs nanowires

We study random telegraph noise in the conductance of InAs nanowire field-effect transistors due to single electron trapping in defects. The electron capture and emission times are measured as functions of temperature and gate voltage for individual traps, and are consistent with traps residing in the few-nanometer-thick native oxide, with a Coulomb barrier to trapping. These results suggest that oxide removal from the nanowire surface, with proper passivation to prevent regrowth, should lead to the reduction or elimination of random telegraph noise, an important obstacle for sensitive experiments at the single electron level.

Red-IR stimulated luminescence in K-feldspar: Single or multiple trap origin?

We investigate on the origins of the infra-red stimulated luminescence (IRSL) signals in 3 potassium feldspars based on IR-red spectroscopy (∼700–1050 nm) using a fiber-coupled tunable Ti:Sapphire laser, in combination with different thermal and optical (pre)treatments of the samples. We also measure dose-response curves with different wavelengths and at different stimulation temperatures so as to be able to distinguish between traps based on their electron trapping cross-sections. Our data suggest that the dosimetric signals, IRSL, and the post IR-IRSL in K-feldspars arise from a single electron trapping centre.

Self-trapping of single and paired electrons in Ge2Se3

We report the theoretical prediction of single and paired electron self-trapping in Ge2Se3. In finite atomic cluster, density functional calculations, we show that excess single electrons in Ge2Se3 are strongly localized around single germanium dimers. We also find that two electrons prefer to trap around the same germanium dimer, rupturing a neighboring Ge–Se bond. Localization is less robust in periodic, density functional calculations. While paired electron self-trapping is present, as shown by wavefunction localization around a distorted Ge–Ge dimer, single-electron trapping is not. This discrepancy appears to depend only on the boundary conditions and not on the exchange–correlation potential or basis set. For single- and paired-electron trapping, we report the adiabatic barriers to motion and we estimate hopping rates and freeze-in temperatures. For the single trapped electron, we also predict the 73Ge and 77Se hyperfine coupling constants.

Single-Electron Transport through Single Dopants in a Dopant-Rich Environment

We show that single-electron transport through a single dopant can be achieved even in a random background of many dopants without any precise placement of individual dopants. First, we observe potential maps of a phosphorus-doped channel by low-temperature Kelvin probe force microscopy, and demonstrate potential changes due to single-electron trapping in single dopants. We then show that only one or a small number of dopants dominate the initial stage of source-drain current vs gate voltage characteristics in scaled-down, doped-channel, field-effect transistors.

Electrical characteristics of Si nanocrystal distributed in a narrow layer in the gate oxide near the gate synthesized with very-low-energy ion beams

A nanocrystal Si (nc-Si) distributed in a narrow layer in the gate oxide close to the gate is synthesized with Si ion implantation at 2keV, and the electrical characteristics of the nc-Si structure are investigated. The onset voltage of the Fowler-Nordheim tunneling of the structure is lower than that of pure SiO2 structure, and it decreases with the nc-Si concentration. The phenomenon is attributed to the reduction of the effective thickness of the tunneling oxide. The application of a positive or negative voltage causes electron or hole trapping in the nc-Si, leading to a positive or negative flatband voltage shift, respectively. A steplike flatband voltage shift as a function of charging voltage is observed, suggesting single electron or hole trapping in the nc-Si at room temperature. On the other hand, the nc-Si structure shows good charge-retention characteristics also.

Room-temperature single-electron effects in silicon nanocrystal memories

In this work, we present an experimental study on the single-electron effects observed at room temperature in silicon nanocrystal memories. The electrical characterization has been performed by means of a purposely designed low noise high bandwidth measurement system. Relevant statistical properties of the threshold voltage shifts induced by single-electron trapping and detrapping in the silicon dots are reported. The kinetics of electron capture and emission is also discussed.

New experimental observations of single electron trapping properties of Si nanoclusters in SRO obtained by LPCVD

It has been proposed that silicon nanoclusters embedded in silicon-rich oxide (SRO) can trap one electron, or one hole. Also, it has been suggested that embedded nanoclusters can be classified into interface and bulk nanoclusters. The possibility of using the characteristic of one electron trapping property in new devices is now under intensive research. In this paper, the charging and discharging properties of silicon-rich oxide layer were studied using an Al/SRO/Si MOS-like structure. The SRO layer was deposited by low pressure chemical vapor deposition, and half of the samples were thermally annealed at 1100°C in N 2 ambient. The measured I–V characteristics show clear current peaks and valleys in low voltage regime. This extraordinary behavior is ascribed to the charge exchange between the embedded nanoclusters in SRO layer and the Si substrate. The valence band of the nanoclusters is supposed to play an important role during the charging and discharging process. C–V measurements were also performed in order to clarify the results. The effect of thermal annealing was explored.

Adventures in attonewton force detection

We report detection of forces as small as 1.4 × 10-18 N in a 1 Hz bandwidth using ultrathin silicon cantilevers operating at liquid helium temperatures. Cantilever fabrication, the importance of surface cleanliness and various measurement issues are discussed. Tip–surface interactions are described, including the detection of single electron trapping–untrapping events. Applications of attonewton force detection for single spin magnetic resonance force microscopy (MRFM) and ultrasensitive magnetometry are discussed.

C-V and G-V Measurements Showing Single Electron Trapping in Nanocrystalline Silicon Dot Embedded in MOS Memory Structure

AbstractWe prepared a SiO2/nanocrystalline Si (nc-Si)/SiO2 sandwich structure. A clear positive shift in C-V and G-V curves due to electrons trapped in nc-Si dots has been observed at room temperature. The peak in conductance around flat band condition indicates that a trap event had occurred where an electron is stored per nc-Si dot. A logarithmic charge loss function is found and this discharging process is independent of the thermal activation mechanism. The longer memory retention time and logarithmic charge loss in the dots are explained by a “built-in” electric field through the tunnel oxide, which varies with time, resulting in a variable tunneling probability. The electric repulsion induced by the built-in electric field hinders the discharging of electrons remained in the dots.

Quantum storage effects in n-AlGaAs/GaAs heterojunction FETs with embedded InAs QDs and localized states induced by Ga-FIB implantation

Quantum storage effects have been studied on novel n-AlGaAs/GaAs heterojunction field-effect transistors (FETs) where electron trapping sites, such as localized states induced by Ga-FIB implantation or self assembled InAs quantum dots (QDs), are embedded between the gate and two-dimensional (2D) electron channel. Charging characteristics involving different types of trap levels distributed spatially have been studied by analyzing the current–voltage (I–V), capacitance–voltage (C–V), and frequency-dependent conductance (G) measurements. Information on the trapping mechanisms of electrons and the distribution of trapping sites has been extracted. We found that the charge injection and extraction on single-electron trapping sites has influence on the single-electron memory operation including the quantized threshold voltage (Vth) shift effects.

Single-Electron Tunneling Devices Based on Silicon Quantum Dots Fabricated by Plasma Process

A study of the electrical properties of multiple tunnel junctions (MTJs) formed in a quasi one-dimensional array of randomly deposited silicon nanocrystals is presented. Nanocrystals are deposited by very-high-frequency (VHF) plasma decomposition of silane. The average dot diameter is 8 nm. The source-drain electrode separation is 30 nm. A gate electrode is employed so that the charge states in quantum dots can be controlled. A study of the source-drain current–voltage (I–V) characteristics with various gate voltages is performed. Coulomb blockade, a Coulomb staircase and Coulomb oscillations are observed at temperatures ranging from 40 K to 150 K. Single electron trapping is observed at 40 K.

Modified signed-digit addition by using binary logic operations and its optoelectronic implementation

In this work, a three-step modified signed-digit (MSD) addition by using binary logic operations is proposed. Each input digit is encoded with two binary bits. Through binary logic operations, all of the weight and transfer digits and the final sum digits represented with the same encoding scheme will be generated. The operations can be performed at each digit position in parallel. In our suggested optical arithmetic and logic unit (ALU), a single electron trapping (ET) device is employed to serve as the binary logic device. This technique based on ET logic possesses the advantage of high signal-to-noise ratio (SNR). The optoelectronic system can be constructed in a simple, compact and general-purpose form.

Parallel optical logic processor and bit slice-full adder using a single electron trapping device

A new method is proposed for implementing logic operations by using a single electron trapping (ET) device. Based on the storage and erasure characteristics of the device, each Boolean logic operation can be performed by the corresponding programming. The encoding method is efficient, since each bit is spatially encoded by a single pixel. The system is simple and the optical elements can be stacked together, so the structure is compact. Furthermore, the logic operations involving three or even more variables can be realized easily with the suggested architecture. All the operations are executed in parallel. As an example, a triple-in binary logic processor is demonstrated to perform bit-slice full additions. Experimental results are given.

Single-electron trapping in sub-μm sized MOSFETs : M. Schultz and H.H. Mueller. Electron Technology, Warsaw, Poland, 1996, 29(1), 5

Single-electron trapping in sub-μm sized MOSFETs : M. Schultz and H.H. Mueller. Electron Technology, Warsaw, Poland, 1996, 29(1), 5

Observation and modelling of RTS in InAlAs/InGaAs/InP HFETs

For the first time we report the observation of random telegraph signals (RTS) in InAlAs/InGaAs/InP HFETs. The RTS show a clear Lorentz spectrum in the frequency domain corresponding to deep traps with an activation energy of ΔE T = 0.34 eV. The amplitude of the RTS is about 10 μV, which is more than could be expected by single electron trapping. For a theoretical explanation of the RTS, we assume a correlated capture and emission process, taking into account the change of the electrostatic potential across the gate-source capacitance. Our results show, that the measured amplitude of the RTS can be well understood, if the traps are located beneath the gate electrode.

Conductance modulation by single-electron trapping in sub-μm MOSFETs

The discrete conductance modulations induced by single-electron trapping in sub-μm MOSFETs frequently exceed 10% of the channel conductance and exhibit a large scatter up to two orders of magnitude. It is shown by computer modeling that these modulation properties can only be caused by a spatial non-uniformity of the channel due to fixed oxide charges. In this work the effect of fixed interface charge, which also spatially modulates the channel conductivity, is investigated in detail.