Single Crystalline Si Layer Research Articles

Growth of single crystalline Si on graphene using RF-MBE: Orientation control with an AlN interface layer

Graphene integration with commonly used Si is very promising for high-performance devices in the future. The fabrication of Si on graphene has gained more attention to realize promising device design and to develop high-quality Si thin-film technology. Nevertheless, attempts to develop Si on graphene are very few, and films are often of poor-quality. Introducing an AlN atomic layers as an interface layer, this paper reports the growth of single crystalline Si on graphene using radio-frequency plasma-assisted molecular beam epitaxy (RF-MBE). We focus on the initial growth process of Si on graphene and clarify the epitaxial relationship between Si and graphene. It is observed that the initial Si nuclei rotate randomly on the surface if deposited directly on the graphene, which implies that orientation control of the initial Si layers on the epitaxial graphene is very important to obtain high-quality layers. The proposed thin AlN intermediate layer to the graphene surface greatly enhances the orientation of initial Si nuclei and results in a single crystalline Si layer on the epitaxial graphene.

Formation of Precipitates in Si Implanted with 64Zn+ and 16O+ Ions

The results of studying the surface Si layer and precipitate formation in CZ n-Si(100) samples sequentially implanted with 64Zn+ ions with a dose of 5 × 1016 cm2 and energy of 100 keV and 16O+ ions with the same dose but an energy of 33 keV at room temperature so that their projection paths Rp = 70 nm would coincide are presented. The post-implantation samples are annealed for 1 h in an inert Ar medium in the temperature range of 400–900°C with a step of 100°C. The profiles of the implanted impurities are studied by time-of-flight secondary ion mass spectrometry. The Si surface is visualized using a scanning electron microscope, while the near-surface layer is visualized with the help of maps of elements formed by Auger electron spectroscopy with profiling over depth. The ZnO(002) texture is formed in an amorphized Si layer after the implantation of Zn and O ions. ZnO(102) crystallites of 5 nm in size are found in a recrystallized single-crystalline Si layer after annealing in Ar at 700°C.

Формирование преципитатов в Si, имплантированном ионами -=SUP=-64-=/SUP=-Zn-=SUP=-+-=/SUP=- и -=SUP=-16-=/SUP=-O-=SUP=-+-=/SUP=-

AbstractThe results of studying the surface Si layer and precipitate formation in CZ n -Si(100) samples sequentially implanted with ^64Zn^+ ions with a dose of 5 × 10^16 cm^2 and energy of 100 keV and ^16O^+ ions with the same dose but an energy of 33 keV at room temperature so that their projection paths R _ p = 70 nm would coincide are presented. The post-implantation samples are annealed for 1 h in an inert Ar medium in the temperature range of 400–900°C with a step of 100°C. The profiles of the implanted impurities are studied by time-of-flight secondary ion mass spectrometry. The Si surface is visualized using a scanning electron microscope, while the near-surface layer is visualized with the help of maps of elements formed by Auger electron spectroscopy with profiling over depth. The ZnO(002) texture is formed in an amorphized Si layer after the implantation of Zn and O ions. ZnO(102) crystallites of 5 nm in size are found in a recrystallized single-crystalline Si layer after annealing in Ar at 700°C.

Varifocal Scanner Using Wafer Bonding

We present a varifocal mirror integrated with a comb-drive scanner (varifocal scanner) fabricated by using a wafer bonding technology. An Au-Au thermocompression bonding technology is utilized for the integration. The bonding technology enables fabricating the multiple single crystalline Si layers on a wafer. The varifocal scanner consists of the three Si layers: 1) the fixed comb layer; 2) the scanner frame layer; and 3) the varifocal mirror layer. The 2-mm-diameter and 10- $\mu \text{m}$ -thick varifocal mirror is fabricated on the $60~\mu \text{m}$ thick comb-drive scanner. The focal length modulation range of the varifocal mirror is from −523 to 139 mm at the frequency of 18.3 kHz. The optical angle is 7° at the resonant frequency of 3.59 kHz. The motion couplings between the varifocal mirror and the scanner are also investigated. [2016-0257]

In-plane thermal conductivity of sub-20 nm thick suspended mono-crystalline Si layers

We measure the thermal conductivity of a 17.5-nm-thick single crystalline Si layer by using a suspended structure developed from a silicon-on-insulator wafer, in which the Si layer bridges the suspended platforms. The obtained value of 19 Wm−1 K−1 at room temperature represents a tenfold reduction with respect to bulk Si. This design paves the way for subsequent lateral nanostructuration of the layer with lithographic techniques, to define different geometries such as Si nanowires, nanostrips or phononic grids. As a proof of concept, nanostrips of 0.5 × 10 μm have been defined by focused ion beam (FIB) in the ultrathin Si layer. After the FIB cutting process with Ga ions at 30 kV and 100 pA, the measured thermal conductivity dramatically decreased to 1.7 Wm−1 K−1, indicating that the structure became severely damaged (amorphous). Re-crystallization of the structure was promoted by laser annealing while monitoring the Raman spectra. The thermal conductivity of the layer increased again to a value of 9.5 Wm−1 K−1 at room temperature, below that of the single crystalline material due to phonon scattering at the grain boundaries.

Optimal design of a spectral readout type planar waveguide-mode sensor with a monolithic structure

Optical planar waveguide-mode sensor is a promising candidate for highly sensitive biosensing techniques in fields such as protein adsorption, receptor-ligand interaction and surface bacteria adhesion. To make the waveguide-mode sensor system more realistic, a spectral readout type waveguide sensor is proposed to take advantage of its high speed, compactness and low cost. Based on our previously proposed monolithic waveguide-mode sensor composed of a SiO2 waveguide layer and a single crystalline Si layer [1], the mechanism for achieving high sensitivity is revealed by numerical simulations. The optimal achievable sensitivities for a series of waveguide structures are summarized in a contour map, and they are found to be better than those of previously reported angle-scan type waveguide sensors.

200 mm Silicon on Porous Layer Substrates Made by the Smart Cut Technology for Double Layer Transfer Applications

Silicon On Porous Layer (SOPL) substrate was elaborated by applying the Smart Cut{trade mark, serif} technology to silicon substrate having a superficial porous Si layer. Porous Si layer morphology was characterized after anodisation process. A single crystalline/porous Si bilayer was transferred onto a handling wafer to form SOI like structure. Subsequent bonding to a final wafer and separation induced in the fragile embedded porous Si layer led to the double-transfer of the single crystalline Si layer. Changes in mechanical properties and chemical composition of the embedded porous silicon layer as a function of the annealing temperature were also determined. Thickness homogeneity of the transferred thin Si layer was estimated after SOPL fabrication and after double-transfer achievement. The perfect crystallinity of the active Si layer was conserved during the whole process. SOI-like structure fabrication and subsequent separation of thin high quality Si film are reported in order to demonstrate adequacy of SOPL with post device post processing substrate removal.

Biaxially Textured Al Film Growth on CaF2 Nanostructures toward a Method of Preparing Single-Crystalline Si Film on Glass Substrates

We report the room temperature growth of biaxially textured Al films and further demonstrate the use of these Al films in preparing single-crystalline Si layers on glass substrates. The formation of the biaxial texture in Al film relies on the existence of the CaF(2) buffer layer prepared using oblique angle physical vapor deposition, which consists of single-crystalline nanorods with caps that are in the form of inverted nanopyramids. The single-crystalline Si film was obtained upon crystallization of the amorphous Si film deposited through physical evaporation on the biaxially textured Al film. This method of preparing single-crystalline Si film on glass substrate is potentially attractive for being employed in silicon technology and in fabrication of low-cost electronic devices.

Ultrathin Si Thin-Film Transistor on Glass

We have studied the fabrication of ultrathin single-crystalline-silicon thin-film transistors (TFTs) on glass. The single-crystalline Si layer was transferred to glass by hydrogen implantation and anodic bonding. The thickness of the silicon-on-glass (SiOG) was controlled down to 10 nm by dry etching. The p-channel SiOG TFTs with 10-nm-thick Si exhibited the field-effect mobility of 134.9 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vmiddots, threshold voltage of -1.5 V, and gate voltage swing of 0.13 V/dec. The TFTs were found to be stable against gate bias stress of +30 or -30 V.

Low Stress Silicon Layer Transfer onto Quartz Through Hydrogen Capture within Si (B/Ge) Buried Layer

An epitaxial single-crystalline Si layer, 715 nm thick, was transferred onto quartz by wafer bonding and diffused-hydrogen ion cutting below 180°C. A sharp interface for trapping hydrogen atoms was created by the epitaxial growth of an undoped silicon layer on top of a boron/germanium-doped silicon layer. An interfacial hydrogen concentration of 1.5 × 10 22 cm ―3 was achieved by exposure to an atmospheric-pressure plasma. Following annealing at 180°C and subsequent mechanically induced crack propagation at room temperature, a smooth (root-mean-square = 1.14 nm), damage-free silicon layer was transferred onto quartz.

Photocarrier radiometric and ellipsometric characterization of ion-implanted silicon wafers

The photocarrier radiometry (PCR) responses of heavily implanted silicon wafers (As+ ion 1×1013–1×1016cm−2) were reported. The experimental dependence of the PCR amplitude on the implant dose was in good agreement with the theoretical prediction calculated with a three-layer PCR model, in which the implanted silicon wafer was assumed to be consisted of an amorphous, a polycrystalline, and a single-crystalline Si layer. The structural, optical, and transport properties of all layers used in the calculations were determined experimentally with spectroscopic ellipsometry (SE), spectrophotometry, and laterally resolved modulated free-carrier absorption to minimize the uncertainties of the theoretical calculations. The dose dependence of the PCR amplitude showed a nonmonotonicity at high dose implantation, as confirmed by the SE measurements.

41.4: AMOLED based on Silicon‐On‐Glass (SiOG) Technology

AbstractWe have demonstrated that the single crystalline silicon films on the glass substrates can be utilized in the conventional mass production lines. The single crystalline Si layers were transferred to the 370 mm × 470 mm glass substrates using Silicon‐On‐Glass (SiOG) technology. Using the thin film transistor backplanes made by conventional CMOS technology, 2.4″ qVGA AMOLED with integrated circuits were successfully fabricated. A completed 2.4″ qVGA AMOLED module shows wide viewing angle (&gt; 170°) and 73% color gamut. The advantages of SiOG technology and its significances will be presented.

Self-organization of semiconductor nanocrystals by selective surface faceting

The formation and ordering of Si nanocrystals in dewetting and agglomeration of the thin single crystalline Si layer in silicon-on-insulator has been investigated using low-energy electron microscopy. The evolution of the Si dewetting and agglomeration is captured in real time, revealing the detailed process for the formation and ordering of the nanocrystals. A surface faceting mechanism governing this self-organized process is proposed and supported with first-principles calculations.

Ion-cutting of Si onto glass by pulsed and direct-current plasma immersion ion implantation

Ion-cutting using plasma immersion ion implantation (PIII) was investigated for the integration of single crystalline Si layers on glass. In PIII, the sample is immersed in a plasma consisting of the ions of interest. A dc (direct current) or ac (alternating current) voltage is then applied to the sample to extract ions from the plasma and implant into the sample. PIII is inherently more efficient for high dose implantation. It was found that p-Si wafers implanted nominally at room temperature with H doses on the order of a few times 1016 cm−2 could be readily bonded to glass substrates with proper surface treatment similar to that used in conventional implantation for ion-cutting. The wafer surface of the as-implanted Si was converted from p-type to n-type. Upon bonding at room temperature, annealing (300 °C), and exfoliation (450 °C), the transferred Si layer on glass and the as-exfoliated surface of the implanted Si wafer remained n-type. Transmission electron microscopic examination showed a highly defective region near the top of the Si layer transferred onto glass due to H implantation. However, the crystalline quality was nearly defect-free in the deeper region of the layer, in spite of the incorporation of other impurities in the region. Annealing at sequentially higher temperatures led to the recovery of p-type conductivity at ∼600–650 °C. The thickness of the transferred layers suggested that the implanted species were mostly H3+ ions from the PIII implanter used in this study. Secondary ion mass spectrometry results showed coimplanted atmospheric impurities such as oxygen, nitrogen, and carbon that affected the electrical properties of the transferred Si layers. dc PIII is demonstrated in this study to be more superior than conventional pulsed PIII for this process and improved vacuum conditions of the implantation chamber are needed to eliminate or reduce impurities.

Single crystal Si layers on glass formed by ion cutting

The process of ion cutting was used to integrate single crystalline Si layers on glass for potential active matrix flat panel display and other applications. It was found that p-Si wafers implanted at 100–150 °C with H with a dose in the order of a few times 1016 cm−2 could be readily bonded to glass substrates when both of the surfaces were properly treated and activated. The as-implanted Si wafer surface was converted from p type to n type. Upon bonding at room temperature, annealing (300 °C) and exfoliation (450 °C), the transferred Si layer on glass and the as-exfoliated surface of the implanted Si wafer remained n type. A highly defective region was observed near the top of the Si layer on glass, however the crystalline quality was nearly defect free in the deeper region of the layer. Annealing at sequentially higher temperatures led to the recovery of p type conductivity at ∼600–650 °C. The type conversion and the subsequent annealing behavior observed on the samples were rationalized in terms of ion enhanced oxygen diffusion and the presence of H-related shallow donors in the Si.

Effect of a vacuum ion gauge on the contamination of a hydrogen‐passivated silicon surface

The effect of operating a vacuum ion gauge on carbonaceous (C) contamination of a hydrogen (H)‐passivated Si surface before epitaxial growth was investigated. The dependence of C contamination on the residence time in the loading chamber, tlc, was determined with or without operating a vacuum ion gauge. The results showed that C contamination of a H‐passivated surface was greatly increased by use of the ion gauge. With ion gauge operation in a vacuum of 1×10−6–1×10−7 Torr in the loading chamber, the configuration of the ion gauge and upside down‐stacked wafers is shown to be a dominant factor of C contamination of the Si surface. The presence of C contaminants could be determined by observing SiC diffraction patterns using in situ reflection high energy electron diffraction (RHEED), since the C contaminants reacted with Si to produce single crystalline SiC at a temperature as high as 850 °C. The RHEED patterns demonstrated that the single crystalline SiC had a zinc‐blende structure. Single crystalline SiC islands with an ellipsoidal cross section were observed by high resolution transmission electron microscopy. In the subsequent epitaxial growth of Si, a well oriented single crystalline Si layer could be grown over the SiC islands although the effect of C contamination on the electrical characteristics of the interface was not clarified. Longer tlc with the ion gauge also required a higher temperature to achieve a 2×1 reconstructed surface structure from the H‐passivated Si surface.

Counter-oxidation of superficial Si in single-crystalline Si on SiO2 structure

This work proposes an oxidation mechanism for single-crystalline Si overlying a buried SiO2 layer (SOI wafer). Experimental results show that not only the surface oxide but also the buried oxide layer of the SOI wafer grows during the thermal oxidation process. The oxidation behavior is analyzed with a simple model including oxygen diffusion through the superficial single crystalline Si layer, which agrees well with the experimental data. Furthermore, oxygen penetration through the superficial Si layer is verified by oxidation experiments using isotope oxygen.

Formation of buried CoSi 2 by ion implantation

High dose 59Co + implantation into Si(111) and Si(100) substrates heated to 350°C and subsequent two-step annealing leads to the formation of buried, epitaxial CoSi 2 layers in Si. Ion channeling, sheet resistivity measurements and transmission electron microscopy were used to study the silicidation and the recrystallization processes. After annealing at 600°C low Omegaic silicide layers were obtained. For the formation of CoSi 2 during the first annealing step we determined an activation energy of 2.8 eV. The second annealing step at about 1000°C results in single crystalline, epitaxial CoSi 2 layers in full alignment with the Si matrix (A/A/A heterostructure). The low resistivity of 13 μΩ cm is indicative of the high quality and high purity of the layers. Due to the lattice mismatch the buried layer is elastically strained. Layers thicker than about 30 nm undergo strain relaxation by generating misfit dislocations. For the planarization of the silicide layer we obtained an activation energy of 3.6 eV. Planarization may occur via Ostwald ripening of isolated CoSi 2 precipitates, or it may occur by a coagulation process. The single crystalline Si layer on top was used as a templated for subsequent growth of epitaxial Si by MBE to bury the silicide deep in Si. Buried metallic lines with a width of several microns were fabricated by implantation using a SiO 2 mask.

4479297 Method of fabricating three-dimensional semiconductor devices utilizing CeO2 and ion-implantation

A method for fabricating a three-dimensional multi-layer integrated circuit of single crystalline CeO 2 and Si is proposed. This method is characterized in that a single crystalline CeO 2 insulation layer, or the like, is formed on a single crystalline Si substrate. An isolation region is formed in the single crystalline Si substrate. The region is transformed into a SiO 2 insulation layer by selectively introducing oxygen ions through the single crystalline CeO 2 insulation layer and reacting the oxygen ions with the single crystalline Si. An epitaxial growth single crystalline Si layer is formed on the single crystalline CeO 2 insulation layer. Predetermined processes, such as forming a single crystalline CeO 2 layer, are performed thereafter to form the three-dimensional structures of semiconductor elements such as MOS transistors and bipolar transistors with high packing density and reliability.