Single Chip Solution Research Articles

Self-Calibratable Absolute Modular Rotary Encoder: Development and Experimental Research.

Advanced microfabrication technologies have revolutionized the field of reflective encoders by integrating all necessary optical components and electronics into a miniature single-chip solution. Contemporary semiconductor sensors could operate at wide tolerance ranges that make them ideal for integration into compact and lightweight modular encoder kit systems. However, in order to achieve the high accuracy of the operating encoder, precise mechanical installation is still needed. To overcome this issue and exploit the full potential of modern sensors, the self-calibratable absolute modular rotary encoder is developed. The equal division average (EDA) method by combining the angular position readings from multiple optical sensors is used to simplify the installation process and ensure the high accuracy of the system. The produced prototype encoder is experimentally tested vs. the reference encoder and the measurement deviations of using different numbers and arrangements of optical sensors are determined. The obtained results show encoder ability to handle the mounting errors and minimize the initial system deviation by more than 90%.

Foundry manufacturing of octave-spanning microcombs.

Soliton microcombs provide a chip-based, octave-spanning source for self-referencing and optical metrology. We use a silicon nitride integrated photonics foundry to manufacture 280 single-chip solutions of octave-spanning microcombs on a wafer. By group-velocity dispersion (GVD) engineering with the waveguide cross section, we shape the soliton spectrum for dispersive-wave spectral enhancements at the frequencies for f-2f self-referencing. Moreover, we demonstrate the other considerations, including models for soliton spectrum design, ultra-broadband resonator external coupling, low-loss edge couplers, and the nonlinear self-interactions of few-cycle solitons. To cover the fabrication tolerance, we systematically scan 336 parameter sets of resonator width and radius, ensuring at least one device on each chip can yield an octave-spanning comb with an electronically detectable carrier-envelope offset frequency, which has been supported by our experiment. Our design and testing process permit highly repeatable creation of single-chip solutions of soliton microcombs optimized for pump operation ∼100 mW and high comb mode power for f-2f detection, which is the central component of a compact microsystem for optical metrology.

Low-loss and polarization insensitive 32 × 4 optical switch for ROADM applications

Integrated switches play a crucial role in the development of reconfigurable optical add-drop multiplexers (ROADMs) that have greater flexibility and compactness, ultimately leading to robust single-chip solutions. Despite decades of research on switches with various structures and platforms, achieving a balance between dense integration, low insertion loss (IL), and polarization-dependent loss (PDL) remains a significant challenge. In this paper, we propose and demonstrate a 32 × 4 optical switch using high-index doped silica glass (HDSG) for ROADM applications. This switch is designed to route any of the 32 inputs to the express ports or drop any channels from 32 inputs to the target 4 drop ports or add any of the 4 ports to any of the 32 express channels. The switch comprises 188 Mach-Zehnder Interferometer (MZI) type switch elements, 88 optical vias for the 44 optical bridges, and 618 waveguide-waveguide crossings with three-dimensional (3D) structures. At 1550 nm, the fiber-to-fiber loss for each express channel is below 2 dB, and across the C and L bands, below 3 dB. For each input channel to all 4 drop/add channels at 1550 nm, the loss is less than 3.5 dB and less than 5 dB across the C and L bands. The PDLs for all express and input channels to the 4 drop/add channels are below 0.3 dB over the C band, and the crosstalk is under −50 dB for both the C and L bands.

H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices

Prior hardware accelerator designs primarily focused on single-chip solutions for 10 MB-class computer vision models. The GB-class transformer models for natural language processing (NLP) impose challenges on existing accelerator design due to the massive number of parameters and the diverse matrix multiplication (MatMul) workloads involved. This work proposes a heterogeneous 3D-based accelerator design for transformer models, which adopts an interposer substrate with multiple 3D memory/logic hybrid cubes optimized for accelerating different MatMul workloads. An approximate computing scheme is proposed to take advantage of heterogeneous computing paradigms of mixed-signal compute-in-memory (CIM) and digital tensor processing units (TPU). From the system-level evaluation results, 10 TOPS/W energy efficiency is achieved for the BERT and GPT2 model, which is about 2.6× ∼ 3.1× higher than the baseline with 7 nm TPU and stacked FeFET memory.

Tuna-step: tunable parallelized step emulsification for the generation of droplets with dynamic volume control to 3D print functionally graded porous materials.

We present tuna-step, a novel microfluidic module based on step emulsification that allows for reliable generation of droplets of different sizes. Until now, sizes of droplets generated with step emulsification were hard-wired into the geometry of the step emulsification nozzle. To overcome this, we incorporate a thin membrane underneath the step nozzle that can be actuated by pressure, enabling the tuning of the nozzle size on-demand. By controllably reducing the height of the nozzle, we successfully achieved a three-order-of-magnitude variation in droplet volume without adjusting the flow rates of the two phases. We developed and applied a new hydrophilic surface modification, that ensured long-term stability and prevented swelling of the device when generating oil-in-water droplets. Our system produced functionally graded soft materials with adjustable porosity and material content. By combining our microfluidic device with a custom 3D printer, we generated and extruded oil-in-water emulsions in an agarose gel bath, creating unique self-standing 3D hydrogel structures with porosity decoupled from flow rate and with composition gradients of external phases. We upscaled tuna-step by setting 14 actuatable nozzles in parallel, offering a step-emulsification-based single chip solution that can accommodate various requirements in terms of throughput, droplet volumes, flow rates, and surface chemistry.

Accelerating AI and Computer Vision for Satellite Pose Estimation on the Intel Myriad X Embedded SoC

The challenging deployment of Artificial Intelligence (AI) and Computer Vision (CV) algorithms at the edge pushes the community of embedded computing to examine heterogeneous System-on-Chips (SoCs). Such novel computing platforms provide increased diversity in interfaces, processors and storage, however, the efficient partitioning and mapping of AI/CV workloads still remains an open issue. In this context, the current paper develops a hybrid AI/CV system on Intel’s Movidius Myriad X, which is an heterogeneous Vision Processing Unit (VPU), for initializing and tracking the satellite’s pose in space missions. The space industry is among the communities examining alternative computing platforms to comply with the tight constraints of on-board data processing, while it is also striving to adopt functionalities from the AI domain. At algorithmic level, we rely on the ResNet-50-based UrsoNet network along with a custom classical CV pipeline. For efficient acceleration, we exploit the SoC’s neural compute engine and 16 vector processors by combining multiple parallelization and low-level optimization techniques. The proposed single-chip, robust-estimation, and real-time solution delivers a throughput of up to 5 FPS for 1-MegaPixel RGB images within a limited power envelope of 2 W.

An Indoor People Counting and Tracking System using mmWave sensor and sub-sensors

The automatic detection and recognition system has many applications in implementing the smart city. Device-based and optical methods perform well in detecting and recognizing people, but several issues remain, such as device limitations, environmental limitations, and privacy concerns. To address these issues, we propose a real-time people counting and tracking system mainly based on a millimeter wave radar (mmWave) as an alternative to optical solutions in restaurants and retail. With the aid of sub-sensors, such as another mmWave radar or camera, this system also may feed the need for static people detection and security. It visualizes customer information, including trajectories and the number of people, helping the restaurant to prevent crowds during the pandemic of COVID-19 and analyzing customer visiting patterns for efficient management and marketing. The mmWave single-chip solution achieves an 83.5 % overall counting accuracy for walking people with a median position error of 0.17 m. The mmWave radar with sub-sensor cameras system approaches an overall detection accuracy of 93.1 %.

Online capacitive detection method for moisture content of aggregate based on edge effect

The moisture content of aggregate has an important influence on the final mix proportion of concrete and the quality of finished products. The detection methods of moisture content include offline and online. At present, the offline oven-dried method which is inefficient is often used for measurement. The capacitance method is easy to implement, low cost, high precision, low power consumption and fast response. However, the traditional capacitance measurement method must ensure that the space inside the plate is full of medium, which is more suitable for offline measurement. In order to realize online measurement, a moisture content detection method of aggregate based on edge effect is proposed. The wear of the plate can be avoided effectively by using the coplanar scattering field capacitive plate combined with the striker plate. The signal processing circuit uses a single chip solution PCAP01 to effectively improve the anti-interference ability of the detection circuit. The developed sensor is suitable for inner water detection of aggregate. The experimental results show that the effective measurement range of the sensor is 0 ∼ 1.0%,the penetration depth is 10 mm, the resolution is 0.1%, the hysteresis error is 2.69%, and the repeatability error is 10.31%.

An Ultra Low Current Measurement Mixed-Signal ASIC for Radiation Monitoring Using Ionisation Chambers

Measurement of total ionizing dose in a radiation field is efficiently carried out by ionisation chambers. The paper details the design of a mixed-signal ASIC for the front-end electronics of ionisation chambers. A single chip solution for ultra-low current measurement is designed by combining the current processing analog section realized using low leakage thick gate transistors and the data handling digital section implemented using fast thin gate transistors. The design succeeds in limiting the cross coupling between the two circuit domains using deep nwells and guard rings. The ASIC fabricated in 130 nm technology attains a wide dynamic range of -7 fA to -20 μA with maximum error in measurement less than ±4 %. The ASIC occupies an area of 3.52 mm2 and has a total power consumption of 17.4 mW. The femtoampere range input leakage current of the ASIC contributed primarily by the ESD diodes was found to be varying exponentially with temperature. Dose rate measurements from 5 μSv/h to 7.4 Sv/h is demonstrated by interfacing the ASIC to an ionisation chamber.

FM-CW compact reflectometer using DDS signal generation

A prototype of a compact coherent fast frequency sweeping RF back-end is being developed at IPFN-IST using commercial Monolithic Microwave Integrated Circuits (MMIC). On this work we present the usability of this concept of compact reflectometry associated with a Direct Digital Synthesis (DDS) source. Flexibility is one of the design goals for the back-end prototype, so that it can easily match the required frequency range. The backend alone covers the NATO J-band (10 GHz to 20 GHz) and is designed to drive external full band frequency multipliers, resulting in an ultra-wideband coverage of up to 140 GHz. FM-CW radar precision is strongly dependent on the probing source linearity. DDS nowadays plays an important role in signal generation in many fields of applications for communication systems as well as in radar technology. Modern DDSs are fully integrated, low-cost, single chip solutions that only need an external clock source for generating sinusoidal output signals up to several gigahertz. The DDS benefits from the totally digital generation of the output signal, which allows full control of the signal’s frequency and phase, both with very high precision and resolution. Recent implementations feature automatic sweeping capability, thus allowing the DDS to generate very linear and agile frequency chirps, assuming a high quality and constant frequency reference clock source. We propose to implement a DDS signal generation solution with the capability of a full band sweep in 1 μs. On the receiver side the IF and reference signals will be digitised allowing the use of high flexible data processing techniques. Input/output signals will allow the synchronisation of several systems.

Stable and Reduced-Linewidth Laser Through Active Cancellation of Reflections Without a Magneto-Optic Isolator

Integrating photonics with CMOS electronics in silicon is essential to enable chip-scale, electronic-photonic systems that will revolutionize classical and quantum communication and computing systems. However, the lack of an on-silicon isolator, capable of blocking unwanted back reflections and ensuring the stable operation of the laser, precluded many previous demonstrations from providing single-chip solutions. For most optical systems employing a laser, magneto-optic isolators have been indispensable, but such isolators are incompatible with silicon. To stabilize on-chip lasers, reflections-cancellation circuits were proposed as a way to reduce the reflections going back to the laser. Yet, a stable laser against time-varying back reflections was never demonstrated. Here we demonstrate a stable quantum well-distributed feedback (QWDFB) laser against slowly time-varying reflections using a reflections-cancellation circuit (RCC) on a foundry-produced, silicon-photonic (SiP) chip. The optical spectrum and the relative intensity noise (RIN) of the laser when the RCC was running is comparable to when an isolator was used. By accurately locking the laser in a stable optical feedback regime, the RCC further enhances the QWDFB laser performance by reducing its linewidth by a factor of 100, down to 3 kHz. Both results are enabled using novel techniques in the design, calibration, tuning, and control of the proposed SiP RCC. The optical insertion loss of the RCC is less than 1.5 dB for reflections smaller than −20 dB and can yield isolation ranges of up to 64 dB. Our device paves the way towards the mass production of fully integrated, low-cost electronic-photonic silicon chips without attaching magneto-optic isolators between the laser and the SiP chip.

Localized Bioimpedance Measurements with the MAX3000x Integrated Circuit: Characterization and Demonstration.

The commercial availability of integrated circuits with bioimpedance sensing functionality is advancing the opportunity for practical wearable systems that monitor the electrical impedance properties of tissues to identify physiological features in support of health-focused applications. This technical note characterizes the performance of the MAX3000x (resistance/reactance accuracy, power modes, filtering, gains) and is available for on-board processing (electrode detection) for localized bioimpedance measurements. Measurements of discrete impedances that are representative of localized tissue bioimpedance support that this IC has a relative error of <10% for the resistance component of complex impedance measurements, but can also measure relative alterations in the 250 m range. The application of the MAX3000x for monitoring localized bicep tissues during activity is presented to highlight its functionality, as well as its limitations, for multi-frequency measurements. This device is a very-small-form-factor single-chip solution for measuring multi-frequency bioimpedance with significant on-board processing with potential for wearable applications.

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.

Single-chip solution for electronics unit of a smart pressure sensor

PurposeDifferential pressure is an important technological parameter, one urgent task of which is control and measurement. To date, the lion’s share of research in this area has focused on the development and improvement of differential pressure sensors. The purpose of this paper is to develop a smart differential pressure sensor with improved operational and metrological characteristics.Design/methodology/approachThe operating principle of the developed pressure sensor is based on the capacitive measurement principle. The measuring unit of the developed pressure sensor is based on a differential capacitive sensitive element. Programmable system-on-chip (PSoC) technology has been used to develop the electronics unit.FindingsThe use of a differential capacitive sensitive element allows the unit to compensate for the influence of interference (for example, temperature) on the measurement result. With the use of PSoC technology, it is also possible to increase the noise immunity of the developed smart differential pressure sensor and provide an unparalleled combination of flexibility and integration of analog and digital functionality.Originality/valueThe use of PSoC technology in the developed smart differential pressure sensor has many indisputable advantages, as the size of the entire circuit can be minimized. As a result, the circuit has improved noise immunity. Accordingly, the procedure for debugging and changing the software of the electronics unit is simplified. These features make development and manufacturing cost effective.

Microring resonator-assisted Fourier transform spectrometer with enhanced resolution and large bandwidth in single chip solution

Single chip integrated spectrometers are critical to bring chemical and biological sensing, spectroscopy, and spectral imaging into robust, compact and cost-effective devices. Existing on-chip spectrometer approaches fail to realize both high resolution and broad band. Here we demonstrate a microring resonator-assisted Fourier-transform (RAFT) spectrometer, which is realized using a tunable Mach-Zehnder interferometer (MZI) cascaded with a tunable microring resonator (MRR) to enhance the resolution, integrated with a photodetector onto a single chip. The MRR boosts the resolution to 0.47 nm, far beyond the Rayleigh criterion of the tunable MZI-based Fourier-transform spectrometer. A single channel achieves large bandwidth of ~ 90 nm with low power consumption (35 mW for MRR and 1.8 W for MZI) at the expense of degraded signal-to-noise ratio due to time-multiplexing. Integrating a RAFT element array is envisaged to dramatically extend the bandwidth for spectral analytical applications such as chemical and biological sensing, spectroscopy, image spectrometry, etc.

The Improved Division-Less MT-Type Velocity Estimation Algorithm for Low-Cost FPGAs

Advanced motion control applications require smooth and highly accurate high-bandwidth velocity feedback, which is usually provided by an incremental encoder. Furthermore, high sampling rates are also demanded in order to achieve cutting-edge system performance. Such control system performance with high accuracy can be achieved easily by FPGA-based controllers. On the other hand, the well-known MT method for velocity estimation has been well proven in practice. However, its complexity, which is related to the inherent arithmetic division involved in the calculus part of the method, prevents its holistic implementation as a single-chip solution on small-size low-cost FPGAs that are suitable for practical optimized control systems. In order to overcome this obstacle, we proposed a division-less MT-type algorithm that consumes only minimal FPGA resources, which makes it proper for modern cost-optimized FPGAs. In this paper, we present new results. The recursive discrete algorithm has been further optimized, in order to improve the accuracy of the velocity estimation. The novel algorithm has also been implemented on the experimental FPGA board, and validated by practical experiments. The enhanced algorithm design resulted in improved practical performance.

A 2.3 &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;W ECG-On-Chip for Wireless Wearable Sensors

This brief presents an ultra-low power single chip solution for electrocardiography (ECG) signal acquisition and processing in wearable ECG sensors. The chip contains a low noise preamplifier with embedded band-pass function, a programmable gain buffer, a 12-bit successive approximation ADC, a novel morphological filter based QRS detector, 8-Kb on-chip SRAM, a control unit and MCU interfaces. The chip was designed and implemented in 0.35- ${\mu }\text{m}$ standard CMOS process. The analog core operates from 0.8 V to 1.8 V, while the digital circuits and SRAM operate from 1.5 V to 3.6 V. The chip has a total core area of 5.74 mm2 and consumes $2.3~{\mu }\text{W}$ . Small size and low power consumption make this chip suitable for usage in wearable ECG sensors. Apart from presenting the measurement results, we also successfully demonstrate a prototype wearable ECG device, for long term cardiac monitoring using the proposed ECG-on-chip.

A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS

Large-scale parallel implementation of matrix multiply and accumulate (MAC) core poses significant energy and area constraints in analog voltage domain under reduced supply voltage. A spatial multi-bit sub-1-V time-domain matrix multiplier interface is presented using multi-bit back-gate-driven delay elements as a scalable alternative for various approximate computing applications. A single-chip solution is demonstrated for two application modes: a high-throughput digitally driven mode for acceleration and a low-energy analog front-end mode for sensing. In accelerate mode, the system achieves an aggregate throughput of 21.6 GMAC/s with 9 TOPS/W energy efficiency. In sense mode, the system exhibits an energy efficiency of 55.3 TOPS/W for classification purpose. The proposed architecture utilizes 16-parallel 6-bit input vectors to perform matrix MAC computations using time-domain signal processing with 3-bit resistive weights at a sub-1-V supply of 0.7 V. An integrated speculative time-to-digital converter (is employed for 6-bit time-domain quantization with an on-chip mismatch calibration scheme. The prototype is fabricated in 65-nm CMOS technology and occupies an active area of 0.04 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The system performs image recognition of handwritten digits using a machine learning scheme and demonstrates an average classification accuracy of 84.3% on the MNIST dataset. The resultant energy per MAC computation in the proposed spatial architecture is about 15× lower than a digital CMOS combinational logic-based parallel-tree MAC.

Single-Chip Design for Intelligent Surveillance System

During recent years, a digital surveillance system has gained more popularity. Object recognition plays a critical role in an intelligent surveillance system. It mainly consists of several vision-based techniques such as segmentation and tracking. However, these techniques are still challenging. In this paper, an intelligent surveillance system has been proposed on the basis of single-chip design. An algorithm development and its hardware implementation are well addressed. Our algorithm accomplishes tracking of moving people through successive frames without using boundary box of object or color cues. Although there is occlusion due to gathering of people and other foreground objects, still the proposed algorithm can deal with such situations. The developed hardware architecture involves several tasks including foreground detection, sliced connected component labeling, object grouping, and object tracking. We use parallel processing on object labeling architecture and give the upper and lower image label values simultaneously. Object grouping and object tracking are also manipulated to improve the performance. The whole system is designed using single-chip solution. It is implemented by TSMC 90-nm library with 18.71-K logic gates, 92.288-kB on-chip memory, and 11.4037-mW low power consumption.

4 × 56 Gb/s High Output Power Electroabsorption Modulated Laser Array With up to 7 km Fiber Transmission in L-Band

We present a novel array of electroabsorption modulated lasers as compact and low-cost single-chip solution for future 200 Gb/s transmitters. The array is designed for high optical output power with semiconductor optical amplifiers at the front side of the chip. A common InGaAlAs-MQW active layer structure allows for simple and cost-effective monolithic integration. On chip RF transmission lines are implemented to bring all electrical contacts to the rear side of the array-chip which supports packaging with short wire bonds. The array operates at four different wavelengths spanning over 7.5 nm in the L-band. Uniformity of each wavelength channel is experimentally proven regarding modulation bandwidth >30 GHz, extinction ratio >7 dB, and output power up to 8 dBm. The influence of the semiconducting optical amplifiers on signal quality is investigated by back to back bit error ratio measurements. In transmission experiments over standard single mode fiber links, the array's performance at 4 × 56 GBd NRZ and 4 × 28 GBd PAM4 is demonstrated and the arrays capability for up to 7 km transmission in case of PAM4 signaling is shown.