Single-chip RF Transceiver Research Articles

A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS

The world’s first single-chip RF transceiver to support 5G sub-6-GHz new radio (NR) and long-term evolution (LTE) E-UTRA New Radio-Dual Connectivity (EN-DC) in 14-nm FinFET CMOS technology is presented. The single-chip transceiver integrates identical primary and diversity receivers (RXs) with seven pipelines for supporting four inter-band carrier aggregation (CA) with three 4 $\times $ 4 MIMO, two independent transmitter (TX) chains, eight frequency synthesizers for RX and TX, and on-chip digitally controlled crystal oscillator (DCXO) to reduce the phase noise and bill of material (BOM) cost. The receiver features 12 single-ended low-noise amplifiers (LNAs) with wideband characteristics. With the help of the proposed pipeline structure and frequency-band switchable transformer, the die size can be reduced despite covering the whole frequency range from 2G to sub-6-GHz 5G NR. It achieves the noise figure (NF) from 6.5 to 9.3 dB, +3-dBm out-of-band (OOB) IIP3, more than +70-dBm OOB IIP2 after calibration. For the transmitter, low RX-band noise and harmonic suppression technique are applied to support surface acoustic wave (SAW)-less architecture, and the bandwidth control of the baseband filter is implemented for the digital pre-distortion (DPD) operation of 100-MHz BW in NR transmit data. The measured error vector magnitudes (EVMs) in 4G and 5G bands of n79 are −39.5 dB at +4-dBm output power and −33.9 dB at +3.06-dBm output power, respectively, and the measured RX-band noise of 2G is −163 dBc at 20-MHz offset. The RX consumes 18 mW at LTE 1-CA mode and the TX consumes 350 mW at n79.

Design of CO<sub>2</sub> Collection Node Based on ZigBee

Precision agriculture relies upon the acquisition and processing of agricultural foundation information initially. One of important techniques of realizing it is the remote wireless low power consumption data collection. This paper employed the ZigBee wireless sensor network technology as well as AVR Atmega8L single-chip microcomputer and RF transceiver CC2530 as core parts, and eventually designed a wireless sensor network node for agriculture information collection. The node can accurately detect the concentration of CO2 in real time. Experiments show that the node works well, collects the data effectively and meets the design requirements

Novel Antenna-in-Package Design in LTCC for Single-Chip RF Transceivers

An antenna-in-package (AiP) design offers an elegant antenna solution to modern single-chip RF transceivers. The AiP design that integrates an antenna or antennas with a single-chip RF transceiver die into a standard surface mounted device represents an innovative and important development in the miniaturization of radio systems in recent years. In this paper, we present a novel AiP design in low temperature cofired ceramic (LTCC) technology for single-chip RF transceivers operating in the 5-GHz band. First, we focus on the design of a microstrip line antenna on an LTCC substrate. Then, a double-resonance technique and a meshed ground plane are proposed to enhance the impedance bandwidth of the microstrip line antenna. Next, the microstrip line antenna is integrated into the novel AiP with emphasis on feeding the microstrip line antenna using the packaging elements of the carried single-chip RF transceiver die. After that, a unique AiP design which supports the operation of differential signal to suit the mainstream design of single-chip RF transceivers in a differential architecture is described. Finally, the performance of the original AiP design is verified by experimental results.

Novel Structure and Fabrication Process for Integrated RF Microelectromechanical-System Technology

This paper describes a novel structure and fabrication process for the integration of several types of RF microelectromechanical-system (MEMS) device, such as switches and varactors having different structures. It also describes an encapsulation technique suitable for the integrated devices to protect movable parts during packaging. An adaptable multilayer structure and its fabrication process, which includes planarization with photosensitive polyimide, are proposed for integration. A capsule structure fabricated using spin-coating film transfer and hot-pressing technology is also proposed for protection. Several types of RF MEMS device were simultaneously fabricated on the same substrate using these techniques. The results confirm that these techniques will pave the way for the development of single-chip RF transceivers with integrated RF MEMS devices.

Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time /spl Sigma//spl Delta/ ADC

This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-/spl mu/m BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (/spl Sigma//spl Delta/) ADC has 84-dB dynamic range over a total bandwidth of /spl plusmn/135 kHz for an active area of 0.4 mm/sup 2/. Hence, most of the channel filtering is realized in a CMOS IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm/sup 2/.

Counting the cost of RF system-on-chip

Single-chip RF transceivers are feasible, but are they commercially desirable? Market evolution and technology costs will play an increasing role in determining the viability of RF system-on-chip designs.

A 1.8-v operation RF CMOS transceiver for 2.4-ghz-band GFSK applications

This paper describes a single-chip RF transceiver LSI for 2.4-GHz-band Gaussian frequency shift-keying applications, such as Bluetooth. This chip uses a 0.18-μm bulk CMOS process for lower current consumption. The LSI consists of almost all the required RF and IF building blocks: a transmit/receive antenna switch, a power amplifier, a low noise amplifier, an image rejection mixer, channel-selection filters, a limiter, a received signal strength indicator, a frequency discriminator, a voltage controlled oscillator, and a phase-locked loop synthesizer. The bandpass filter for channel selection was difficult to achieve since it operates at a low supply voltage. However, because large interference is roughly rejected at the output of the image rejection mixer and a wide-input-range bandpass filter with an optimized input bias is realized, the transceiver can operate at a supply voltage of 1.8 V. In the IF section, we adopted a circuit design using the minimum number of passive elements, resistors and capacitors, for a lower chip area of 10.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

MEMS TECHNOLOGY FOR ADVANCED TELECOMMUNICATION APPLICATIONS

MEMS (Micro Electro Mechanical Systems) technology is becoming a crucial enabling technology for optical and RF telecommunication applications due to the performance, cost and integration advantages. All-optical switches and silicon optical benches for optical network systems and RF MEMS components such as RF MEMS switches, tunable capacitors, high Q inductors, and thin film bulk acoustic resonators for miniaturized single chip RF transceivers are discussed. Despite all the promising aspects, practical problems to be addressed for successful commercialization are not trivial. By reviewing optical and RF MEMS research activities and some of the implementation examples, key success factors of MEMS components for the commercialization are discussed.