Single Byte Research Articles

Sensitive remote homology search by local alignment of small positional embeddings from protein language models

Accurately detecting distant evolutionary relationships between proteins remains an ongoing challenge in bioinformatics. Search methods based on primary sequence struggle to accurately detect homology between sequences with less than 20% amino acid identity. Profile- and structure-based strategies extend sensitive search capabilities into this twilight zone of sequence similarity but require slow pre-processing steps. Recently, whole-protein and positional embeddings from deep neural networks have shown promise for providing sensitive sequence comparison and annotation at long evolutionary distances. Embeddings are generally faster to compute than profiles and predicted structures but still suffer several drawbacks related to the ability of whole-protein embeddings to discriminate domain-level homology, and the database size and search speed of methods using positional embeddings. In this work, we show that low-dimensionality positional embeddings can be used directly in speed-optimized local search algorithms. As a proof of concept, we use the ESM2 3B model to convert primary sequences directly into the 3D interaction (3Di) alphabet or amino acid profiles and use these embeddings as input to the highly optimized Foldseek, HMMER3, and HH-suite search algorithms. Our results suggest that positional embeddings as small as a single byte can provide sufficient information for dramatically improved sensitivity over amino acid sequence searches without sacrificing search speed.

Sensitive remote homology search by local alignment of small positional embeddings from protein language models.

Accurately detecting distant evolutionary relationships between proteins remains an ongoing challenge in bioinformatics. Search methods based on primary sequence struggle to accurately detect homology between sequences with less than 20% amino acid identity. Profile- and structure-based strategies extend sensitive search capabilities into this twilight zone of sequence similarity but require slow pre-processing steps. Recently, whole-protein and positional embeddings from deep neural networks have shown promise for providing sensitive sequence comparison and annotation at long evolutionary distances. Embeddings are generally faster to compute than profiles and predicted structures but still suffer several drawbacks related to the ability of whole-protein embeddings to discriminate domain-level homology, and the database size and search speed of methods using positional embeddings. In this work, we show that low-dimensionality positional embeddings can be used directly in speed-optimized local search algorithms. As a proof of concept, we use the ESM2 3B model to convert primary sequences directly into the 3D interaction (3Di) alphabet or amino acid profiles and use these embeddings as input to the highly optimized Foldseek, HMMER3, and HH-suite search algorithms. Our results suggest that positional embeddings as small as a single byte can provide sufficient information for dramatically improved sensitivity over amino acid sequence searches without sacrificing search speed.

An efficient heuristic power analysis framework based on hill-climbing algorithm

Traditional nonprofiling side-channel analysis frequently adopts divide-and-conquer strategy to recover the secret key of a cryptographic algorithm. Only a single key byte is used, whereas the remaining bytes are considered extraneous noise. If the cryptographic algorithm is implemented in hardware with parallel processing, the strategy will lead to the inefficient use of information. The combination of intelligent algorithms and side-channel analysis offers a different idea for nonprofiling methods for parallel hardware implementations. It transforms the problem of key recovery into key optimization. In this paper, we adopt this idea and propose an efficient heuristic framework to assist correlation power analysis. The multipoint hill-climbing algorithm will be used to find the optimal key candidates with higher scores, and the correct key will be found in the optimal key candidates by key enumeration. Multiple bytes of the secret key are used to take full advantage of the helpful information. Besides, two search strategies are introduced to overcome the efficiency problem, and two key enumeration strategies are introduced to solve the key recovery problem when the traces are insufficient. Experimental results on the public DPA Contest V1 dataset show that the heuristic framework performs better than other classical methods, verifying its effectiveness.

A Low-Cost Hardware/Software Platform for Lossless Real-Time Data Acquisition from Imaging Spectrometers.

In real-time data-intensive applications, achieving real-time data acquisition from sensors and simultaneous storage with the necessary performance is challenging, especially if "no-data-lost" requirements are present. Ad hoc solutions are generally expensive and suffer from a lack of modularity and scalability. In this work, we present a hardware/software platform built using commercial off-the-shelf elements, designed to acquire and store digitized signals captured from imaging spectrometers capable of supporting real-time data acquisition with stringent throughput requirements (sustained rates in the boundaries of 100 MBytes/s) and simultaneous information storage in a lossless fashion. The correct combination of commercial hardware components with a properly configured and optimized multithreaded software application has satisfied the requirements in determinism and capacity for processing and storing large amounts of information in real time, keeping the economic cost of the system low. This real-time data acquisition and storage system has been tested in different conditions and scenarios, being able to successfully capture 100,000 1 Mpx-sized images generated at a nominal speed of 23.5 MHz (input throughput of 94 Mbytes/s, 4 bytes acquired per pixel) and store the corresponding data (300 GBytes of data, 3 bytes stored per pixel) concurrently without any single byte of information lost or altered. The results indicate that, in terms of throughput and storage capacity, the proposed system delivers similar performance to data acquisition systems based on specialized hardware, but at a lower cost, and provides more flexibility and adaptation to changing requirements.

Profiling Deep Learning Side-Channel Attacks Using Multi-Label against AES Circuits with RSM Countermeasure

Deep learning side-channel attacks (DL-SCAs) have been actively studied in recent years. In the DL-SCAs, deep neural networks (DNNs) are trained to predict the internal states of the cryptographic operation from the side-channel information such as power traces. It is important to select suitable DNN output labels expressing an internal states for successful DL-SCAs. We focus on the multi-label method proposed by Zhang et al. for the hardware-implemented advanced encryption standard (AES). They used the power traces supplied from the AES-HD public dataset, and reported to reveal a single key byte on conditions in which the target key was the same as the key used for DNN training (profiling key). In this paper, we discuss an improvement for revealing all the 16 key bytes in practical conditions in which the target key is different from the profiling key. We prepare hardware-implemented AES without SCA countermeasures on ASIC for the experimental environment. First, our experimental results show that the DNN using multi-label does not learn side-channel leakage sufficiently from the power traces acquired with only one key. Second, we report that DNN using multi-label learns the most of side-channel leakage by using three kinds of profiling keys, and all the 16 target key bytes are successfully revealed even if the target key is different from the profiling keys. Finally, we applied the proposed method, DL-SCA using multi-label and three profiling keys against hardware-implemented AES with rotating S-boxes masking (RSM) countermeasures. The experimental result shows that all the 16 key bytes are successfully revealed by using only 2,000 attack traces. We also studied the reasons for the high performance of the proposed method against RSM countermeasures and found that the information from the weak bits is effectively exploited.

A Novel Design Methodology to Realize a Single Byte Chipless RFID Tag by Loading a Square Open-Loop Resonator With Micro-Metallic Cells

In this paper, a unique structural design methodology for chipless radio-frequency identification (RFID) tags in frequency domain is presented. The tag geometry is developed by loading an open-loop resonator with micro-metallic-cells (MMC). The realization give rise to a checkerboard resonator type with electromagnetic signatures in its radar cross section that are extremely efficient to manipulate. The resonators layout is distributed on either side of a Rogers substrate to double its coding density. The proposed chipless RFID tag has a memory of 8-bits in total. The operating band of the tag is 6.5-10.5 GHz. The tag has a high bit coding density of 10.94 bits/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and spectral efficiency of 2 bits/GHz. The tag has a very compact size of 17.4 × 4.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The simple structuring methodology and efficient resonators layout will give RFID system designers the flexibility to apply the proposed tag in a wide range of modern applications.

Uncertainty Analysis in Cryptographic Key Recovery for Machine Learning-Based Power Measurements Attacks

The present work concerns side-channel attacks on cryptographic devices protected with the advanced encryption standard. In this regard, the assessment of guessing entropy and the related uncertainty is proposed for machine learning-based attacks based on power measurements. For the first time, the guessing entropy was assessed on the entire key while uncertainty was introduced in the field of side-channel attacks, thus allowing a more rigorous vulnerability test for a device. Notably, a state-of-the-art attack relying on a multilayer perceptron is exploited for classifying power traces leaked from physically accessible devices. A public database was exploited for the sake of results reproducibility. Thanks to cross-validation, the uncertainty associated with retrieving a single key byte can be quantified and then propagated to the entire key by means of the Monte Carlo method. It is thus shown that, when exploiting about 4000 attack records (traces), there is a 10% probability to retrieve the secret key as a whole with less than ten attempts. This implies that a full cryptographic key can be discovered on average ten times for every 100 similar devices by a side-channel attack. This poses security threats particularly relevant in an internet-of-things scenario and addresses the need for improved vulnerability testing and proper countermeasures.

B2-Tree: Page-Based String Indexing in Concurrent Environments

Recently proposed index structures, that combine trie-based and comparison-based search mechanisms, considerably improve retrieval throughput for in-memory database systems. However, most of these index structures allocate small memory chunks when required. This stands in contrast to block-based index structures, that are necessary for disk-accesses of beyond main-memory database systems such as Umbra. We therefore present the B2-tree. The outer structure is identical to that of an ordinary B+-tree. It still stores elements in a dense array in sorted order, enabling efficient range scan operations. However, B2-tree is composed of multiple trees, each page integrates another trie-based search tree, which is used to determine a small memory region where a sought entry may be found. An embedded tree thereby consists of decision nodes, which operate on a single byte at a time, and span nodes, which are used to store common prefixes. This architecture usually accesses fewer cache lines than a vanilla B+-tree as shown in our performance evaluation. As a result, the B2-tree answers point queries considerably faster. Concurrent access to B2-tree pages are managed by an optimistic locking protocol which results in high utilization of the available hardware resources. Our evaluation of read-write workloads attests more than competitive performance for the B2-tree compared to a traditional B+-tree.

A method for fault recognition in the last three rounds of Advanced Encryption Standard

A large number of studies are there for Advanced Encryption Standard (AES) fault attack analysis, but less for fault recognition. This paper presents a recognition method for single-byte fault which is induced in the last three rounds of AES. Studying the differential characteristics of Sbox, the single byte fault induced in ninth round or tenth round will be identified respectively with 9.3 and 9.1 ciphertexts. For the fault induced in eighth round, the fault value can be obtained with 188.5 ciphertexts by analyzing the differential features of two Sboxes and MixColumns. As an auxiliary means for fault attacks, this method is used to realize the byte or bit level physical positioning of confidential data in the encryption chip, which is beneficial to reduce the blindness of the attacker's experiments and obtain the sensitive area of fault attack.

Device Discovery and Context Registration in Static Context Header Compression Networks

Due to the limited bandwidth of Low-Power Wide-Area Networks (LPWAN), the application layer is currently often tied straight above the link layer, limiting the evolution of sensor networks distributed over a large area. Consequently, the highly efficient Static Context Header Compression (SCHC) standard was introduced, where devices can compress the IPv6 and upper layer protocols down to a single byte. This approach, however, assumes that every compression context is distributed before deployment, again limiting the evolution of such networks. Therefore, this paper presents two context registration mechanisms leveraging on the SCHC adaptation layer. This is done by analyzing current registration solutions in order to find limitations and optimizations with regard to very constrained networks. Both solutions and the current State-of-The-Art (SoTA) are evaluated in a Lightweight Machine to Machine (LwM2M) environment. In such situation, both developed solutions decrease the energy consumption already after 25 transmissions, compared with the current SoTA. Furthermore, simulations show that Long Range (LoRa) devices still have a 80% chance to successfully complete the registration flow in a network with a 50% Packet Error Ratio. Briefly, the work presented in this paper delivers bootstrapping tools to constrained, SCHC-enabled networks while still being able to reduce energy consumption.

Speeding up Natural Language Text Search using Compression

Text search is a well-known problem in computer science where the valid shifts of a pattern P in a text string T are found. This paper shows how to speed up text search by searching for P in a compressed version of T. A fast compression algorithm was designed for this aim. This algorithm is based on the assumption that T is restricted to the letters of a single natural language. Relying on this assumption, a letter, in T or P, is encoded into a single byte instead of the two-byte unicode which shortens the string on which a text search algorithm works. The main disadvantage of this approach is the restriction of the alphabet of T to be from a single natural language. However, wide range of text documents comply to this assumption. Another issue is the overhead that is required to compress P and T, but it was found that the proposed compression algorithm is so fast such that its run-time can be paid for and still save text search time. Different approaches to store compressed T are also explored. The conducted experimental study showed that this approach does actually reduce the text search time.

Self-powered signal processing system for visible light communication based on solar panels

We propose a self-powered signal processing system that can transfer a single byte of data without needing any external power supply. The proposed system uses a local extreme point reconstruction algorithm for reconstructing the waveform. In addition, we use Manchester coding in the proposed method for reducing the byte error rate. The experimental results show that the self-powered processor needs 3 mW generated from the solar panel to maintain 1 MSa / s and 8-bit sample depth when the visible light communication link distance is fixed as 30 cm. The maximum bit rate is 500 kbit / s and the corresponding byte error rate is 6 × 10 − 2.

Sanity vs. Invisible Markings

Invisible and near-invisible markings bring us to the human part of the problem?not that code editor authors aren’t human, but most of us will not write new editors, though all of us will use editors. As we all know, once upon a time computers had small memories and the difference between a tab, which is a single byte, and a corresponding number of spaces (8) could be a significant difference between the size of source code stored on a precious disk, and also transferred, over whatever primitive and slow bus, from storage into memory.

MeltdownDetector: A runtime approach for detecting meltdown attacks

In this work, we present a runtime approach, called MeltdownDetector, for detecting, isolating, and preventing ongoing Meltdown attacks that operate by causing segmentation faults. Meltdown exploits a hardware vulnerability that allows a malicious process to access memory locations, which do not belong to the process, including the physical and kernel memory. The proposed approach is based on a simple observation that in order for a Meltdown attack to be worthwhile, either a single byte of data located at a particular memory address or a sequence of consecutive memory addresses (i.e., sequence of bytes) need to be read, so that a meaningful piece of information can be extracted from the data leaked. MeltdownDetector, therefore, monitors segmentation faults occurring at memory addresses that are close to each other and issues a warning at runtime when these faults become “suspicious.” Furthermore, MeltdownDetector flushes the cache hierarchy after every suspicious segmentation fault, which, in turn, prevents any information leakage. In the experiments, MeltdownDetector successfully detected all the attacks and correctly pinpointed all the malicious processes involved in these attacks and did so without issuing any false alarms and without leaking even a single byte of data. Furthermore, the runtime overhead of the fastest MeltdownDetector implementation was about 1%, on average.

A Novel Multi-Objective Electromagnetic Analysis Based on Genetic Algorithm.

Correlation electromagnetic analysis (CEMA) is a method prevalent in side-channel analysis of cryptographic devices. Its success mostly depends on the quality of electromagnetic signals acquired from the devices. In the past, only one byte of the key was analyzed and other bytes were regarded as noise. Apparently, other bytes’ useful information was wasted, which may increase the difficulty of recovering the key. Multi-objective optimization is a good way to solve the problem of a single byte of the key. In this work, we applied multi-objective optimization to correlation electromagnetic analysis taking all bytes of the key into consideration. Combining the advantages of multi-objective optimization and genetic algorithm, we put forward a novel multi-objective electromagnetic analysis based on a genetic algorithm to take full advantage of information when recovering the key. Experiments with an Advanced Encryption Standard (AES) cryptographic algorithm on a Sakura-G board demonstrate the efficiency of our method in practice. The experimental results show that our method reduces the number of traces required in correlation electromagnetic analysis. It achieved approximately 42.72% improvement for the corresponding case compared with CEMA.

Cellular automata-based byte error correction in QCA

It is important for Quantum-dot Cellular Automata (QCA) systems to reliably communicate with other circuits. In this work, we detail a circuit designed in QCA that corrects single byte errors. The circuit implements a Reed–Solomon code and was designed using principles from Cellular Automata (CA) theory. We present an encoder and a decoder that are able to correct single byte errors. Moreover, we also design other building blocks such as: pulse generator, syndrome calculator, position locator, word inverter, and error corrector circuits. We also include an application example, demonstrating how to use and connect the encoder and decoder in QCA communication systems. We validate the design by means of simulations in QCADesigner. Our results show the correct behavior of the circuit, being able to detect and correct a byte error. We also present the cost function and energy dissipation analysis of the system. The proposed circuit is of fundamental importance as it can be used and applied in QCA communications systems, improving its robustness in the presence of communication errors.

Fault analysis of AEZ

SummaryAEZ is a block cipher mode based on AES which uses three 128‐bit keys. The algorithm has been updated several times during the three rounds of the CAESAR cryptographic competition. Cryptanalytic results presented on AEZ to date do not breach its security. This paper describes a fault injection analysis on AEZ. We focus on analysing AEZ v4.2 but also investigate the applicability of these analyses to the recent version AEZ v5. This paper shows that all three 128‐bit keys in AEZ v4.2 can be uniquely retrieved using only three random‐valued single byte fault injections. A similar approach using four fault injections can uniquely recover all three keys of AEZ v5. The feasibility of this fault injection methodology has been proven against AES in previous works.

Compact CA-Based Single Byte Error Correcting Codec

Memory contents are usually corrupted due to soft errors caused by external radiation and hence the reliability of memory systems is reduced. In order to enhance the reliability of memory systems, error correcting codes (ECC) are widely used to detect and correct errors. Single bit error correcting with double bits errors detecting codes are generally used in memory systems. But in case of multiple cell errors, these codes are unable to detect and correct errors. Recently, single byte error correcting Reed Solomon (SEC-RS) codes are used to detect and correct single byte error in memory systems. In this paper, a new single byte error correcting (SEC) code is proposed based on the concept of cellular automata (termed as CASEC). The main aim of this work is to reduce the area and power of SEC encoder and decoder circuit without affecting delay. In this paper, CASEC(10,8,8), CASEC(18,16,8), 2xCASEC(10,8,4) and 2xCASEC(19,6,4) codecs are designed and implemented. CASEC(18,16,8) codec has 67.79 percent lesser hardware complexity compared to existing design. Proposed codecs are simulated and synthesized for both FPGA and ASIC platforms. It is found that speed of the proposed design is almost equal to the existing design but requires lesser area and power. Area-delay product (ADP) of proposed CASEC(10,8,8), CASEC(18,16,8), 2xCASEC(10,8,4) codecs are better compared to the existing designs.

Multi-Byte Power Analysis: A Generic Approach Based on Linear Regression

Linear regression used to be known as a robust side-channel analysis (SCA) method as it makes use of independent bits leakage. This leakage assumption is more general than Hamming weight/Hamming distance model used in correlation power analysis (CPA). We find that in many common scenarios, linear regression is not only an alternative but also a more efficient tool compared with CPA. This paper proposes a generic SCA approach based on linear regression called multi-byte power analysis (MPA) that can be applied to any number of bytes instead of one single byte when performing SCA. Two typical cases are illustrated in this paper. One is recovering keys with XOR operation leakage and the other one is chosen plaintext attack on block ciphers with leakages from round output. Simulation results are given to compare with traditional CPA in both cases. MPA achieves up to 400% and 300% improvements for the corresponding case compared with CPA, respectively. Experiments with AES on SAKURA-G board also prove the efficiency of MPA in practice, where 128 key bits are recovered with 1500 traces using XOR operation leakage and one key byte is recovered with only 50 chosen-plaintext traces in the other case.

Forward Observer system for radar data workflows: Big data management in the field

There are unique challenges in managing data collection and management from instruments in the field in general. These issues become extreme when “in the field” means “in a plane over the Antarctic”. In this paper we present the design and function of the Forward Observer a computer cluster and data analysis system that flies in a plane in the Arctic and Antarctic to collect, analyze in real time, and store Synthetic Aperture Radar (SAR) data. SAR is used to analyze the thickness and structure of polar ice sheets. We also discuss the processing of data once it is returned to the continental US and made available via data grids. The needs for in-flight data analysis and storage in the Antarctic and Arctic are highly unusual, and we have developed a novel system to meet those needs.We describe the constraints and requirements that led to the creation of this system and the general functionality which it applies to any instrument. We discuss the main means for handling replication and creating checksum information to ensure that data collected in polar regions are returned safely to mainland US for analysis. So far, not a single byte of data collected in the field has failed to make it home to the US for analysis (although many particular data storage devices have failed or been damaged due to the challenges of the extreme environments in which this system is used).While the Forward Observer system is developed for the extreme situation of data management in the field in the Antarctic, the technology and solutions we have developed are applicable and potentially usable in many situations where researchers wish to do real time data management in the field in areas that are constrained in terms of electrical supply.