Single-bit Sigma-delta Modulator Research Articles

Implementation and Performance Evaluation of the Frequency-Domain-Based Bit Flipping Controller for Stabilizing the Single-Bit High-Order Interpolative Sigma Delta Modulators

This paper is an extension of the existing works on the frequency-domain-based bit flipping control strategy for stabilizing the single-bit high-order interpolative sigma delta modulator. In particular, this paper proposes the implementation and performs the performance evaluation of the control strategy. For the implementation, a frequency detector is used to detect the resonance frequencies of the input sequence of the sigma delta modulator. Then, a neural-network-based controller is used for finding the solution of the integer programming problem. Finally, the buffers and the combinational logic gates as well as an inverter are used for implementing the proposed control strategy. For the performance evaluation, the stability region in terms of the input dynamical range is evaluated. It is found that the control strategy can significantly increase the input dynamical range from 0.24 to 0.58. Besides, the control strategy can be applied to a wider class of the input signals compared to the clipping method.

Third-order Single-bit Sigma Delta modulator structure for an RF reception chain for a LTE network

Third-order Single-bit Sigma Delta modulator structure for an RF reception chain for a LTE network

Adjustable Nyquist-rate System for Single-Bit Sigma-Delta ADC with Alternative FIR Architecture

ABSTRACTThis paper presents a new smart and compact system dedicated to control the output sampling frequency of an analogue-to-digital converters (ADC) based on single-bit sigma-delta (ΣΔ) modulator. This system dramatically improves the spectral analysis capabilities of power network analysers (power meters) by adjusting the ADC’s sampling frequency to the input signal’s fundamental frequency with a few parts per million accuracy. The trade-off between straightforwardness and performance that motivated the choice of the ADC’s architecture are preliminary discussed. It particularly comes along with design considerations of an ultra-steep direct-form FIR that is optimised in terms of size and operating speed. Thanks to compact standard VHDL language description, the architecture of the proposed system is particularly suitable for application-specific integrated circuit (ASIC) implementation-oriented low-power and low-cost power meter applications. Field programmable gate array (FPGA) prototyping and experimental results validate the adjustable sampling frequency concept. They also show that the system can perform better in terms of implementation and power capabilities compared to dedicated IP resources.

Mixed baseband architecture based on FBD ΣΔ–based ADC for multistandard receivers

<p>This paper presents the design and simulation results of a novel mixed baseband stage for a frequency band decomposition (FBD) analog-to-digital converter (ADC) in a multistandard receiver. The proposed FBD-based ADC architecture is flexible with programmable parallel branches composed of discrete time (DT) 4<sup>th</sup> order single-bit Sigma-Delta modulators. The mixed baseband architecture uses a single non-programmable anti-aliasing filter (AAF) avoiding the use of an automatic gain control (AGC) circuit. System level analysis proved that the proposed FBD architecture satisfies design specifications of the software defined radio (SDR) receiver. In this paper, the authors focus on the Butterworth AAF filter design for a multistandard receiver. Besides, theoretical analysis of the reconstruction stage for UMTS test case is discussed. It leads to a complicated system of equations and high digital filter orders. To reduce the digital reconstruction stage complexity, the authors propose an optimized digital reconstruction stage architecture design. The demodulation-based digital reconstruction stage using two decimation stages has been implemented using MATLAB/SIMULINK. Technical choices and performances are discussed. The computed signal-to-noise ratio (SNR) of the MATLAB/SIMULINK FBD ADC model is equal to at least 75 dB which satisfies the dynamic range required for UMTS signals. Next to hardware implementation with quantized filters coefficients, the authors implemented their proposition in VHDL in a SysGen environment. The measured SNR of the hardware implementation is equal to 74.08 dB which satisfies the required dynamic range of UMTS signals.</p>

A Low-Power Configurable Neural Recording System for Epileptic Seizure Detection

This paper describes a low-power configurable neural recording system capable of capturing and digitizing both neural action-potential (AP) and fast-ripple (FR) signals. It demonstrates the functionality of epileptic seizure detection through FR recording. This system features a fixed-gain, variable-bandwidth (BW) front-end circuit and a sigma-delta ADC with scalable bandwidth and power consumption. The ADC employs a 2nd-order single-bit sigma-delta modulator (SDM) followed by a low-power decimation filter. Direct impulse-response implementation of a sinc(3) filter and 8-cycle data pipelining in an IIR filter are proposed for the decimation filter design to improve the power and area efficiency. In measurements, the front end exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of BW, 5.86- μVrms input-referred noise, and 2.4- μW power consumption in AP mode, while showing 38.5-dB DC gain, 250 to 486 Hz of BW, 2.48- μVrms noise, and 4.5- μW power consumption in FR mode. The noise efficiency factor (NEF) is 2.93 and 7.6 for the AP and FR modes, respectively. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588- μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6- μm CMOS process. The die size is 11.25 mm(2).

Extending the Stable Input Range of a Single-Bit Sigma-Delta Modulator with a Saturation Element

This paper presents a simple compensation scheme for extending the stable input range of a single-bit sigma-delta (Σ-Δ) modulator that is normally stabilized in sliding mode. The proposed control scheme requires a saturation element that provides additional feedback to modify and stabilize the modulator loop filter when the modulator is going to lose stability due to large input level. The proposed compensation scheme is easy to implement and is only activated when the input level is exceedingly large, so it does not affect the performance of the modulator with its input in the normal range. A third-order sigma-delta modulator with an extended input range was designed and implemented to demonstrate the practicality of the proposed design. 

A Performance Prediction Method with an Equation-Based Behavioral Model for a Single-Bit Single-Loop Sigma-Delta Modulator

An equation-based behavioral model has been developed to predict the real performance of a single–loop single-bit Sigma Delta Modulator (SDM). By using this prediction flow, not only can the circuit specifications be acquired, including the gain, bandwidth, slew rate of the OPAMPs, and the capacitor value in the switched-capacitor circuits, but the real performance of the SDM can also be predicted. The switched-capacitor circuits according to the required circuit specifications are employed to design a fourth-order feed-forward (FF) SDM with an over-sampling ratio (OSR) of 64 and a bandwidth of 10kHz using a TSMC 0.35µm CMOS process. The measurement results reveal that the SDM with an input frequency of 2.5kHz and a supply voltage of 3.3V can achieve a dynamic range of 90dB and a spurious-free dynamic range (SFDR) of 85dB under the signal bandwidth of 10kHz and a sampling frequency of 1.28MHz, respectively. The precision of the equation-based behavioral model has been validated by experimental measurements, and its inaccuracy is less than 4%.

A 99-dB DR Fourth-Order Delta–Sigma Modulator for 20-kHz Bandwidth Sensor Applications

A fourth-order single-bit delta-sigma modulator is presented for sensor applications. The loop filter is composed of both feedback and feedforward paths, and the modulator is implemented using fully differential switched-capacitor techniques. A test chip was fabricated in a 0.18-mum standard complementary metal-oxide semiconductor (CMOS) process. The chip core area is 1.22 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and its power consumption is 5.6 mW from a 3.0-V power supply. Measurement results show that a maximum 99-dB dynamic range is achievable at a clock rate of 3.2 MHz for the 20-kHz bandwidth. The designed chip is targeted for high-accuracy and wide-bandwidth sensor applications such as the resistor-based current sensors and the Hall-effect sensors in motor control systems.

VLSI Potentiostat Array With Oversampling Gain Modulation for Wide-Range Neurotransmitter Sensing

A 16-channel current-measuring very large-scale integration (VLSI) sensor array system for highly sensitive electrochemical detection of electroactive neurotransmiters like dopamine and nitric-oxide is presented. Each channel embeds a current integrating potentiostat within a switched-capacitor first-order single-bit delta-sigma modulator implementing an incremental analog-to-digital converter. The duty-cycle modulation of current feedback in the delta-sigma loop together with variable oversampling ratio provide a programmable digital range selection of the input current spanning over six orders of magnitude from picoamperes to microamperes. The array offers 100-fA input current sensitivity at 3.4-muW power consumption per channel. The operation of the 3 mm times3 mm chip fabricated in 0.5-mum CMOS technology is demonstrated with real-time multichannel acquisition of neurotransmitter concentration.

An approach for stability analysis of a single-bit high-order digital sigma-delta modulator

In this work we considered the stability of a single-bit high-order sigma-delta modulator under dc input. A new approach for stability analysis is proposed. A nonlinear circle map is suggested to model the dynamics of the modulator. An analogy between the dynamics of the sigma-delta modulator and the sinusoidal digital phase-locked loop (DPLL) is studied and an approximate fixed point solution is presented with stability criteria. Suggestions for designing stabilized high-order systems are presented.

Stability and Performance of Single-Bit Sigma-Delta Modulators Operated in Quasi-Sliding Mode

Single-bit sigma-delta modulators operated in the quasi-sliding mode are investigated. Sufficient conditions for the existence and stability of this mode of operation are derived. The derived stability conditions, along with an accurate prediction of its performance, enable a high-order modulator to be exactly designed. A fifth-order modulator is designed to convert audio-band signals with an effective resolution of 20 bits to demonstrate the effectiveness of the proposed analysis and method of design.

Analysis and design of single-bit sigma-delta Modulators using the theory of sliding modes

The existence and stability conditions for a single-bit sigma-delta modulator operated in sliding mode are derived. Based on these conditions, a stable single-bit modulator of arbitrary order is synthesized. Also, an alternative interpretation on the modulator's noise-shaping mechanism is presented. From the sliding mode aspect, the modulator is regarded as a device that performs frequency-weighted minimization of the modulation error, and the modulator's loop filter as the weighting function. The noise-shaping equation derived from this aspect helps precisely predict the modulator performance. A fifth-order 2.2-MHz wide-band modulator with an effective resolution of 17 bits is designed as an illustrative example. The simulation result conforms the accuracy of the analysis. In the end, this paper presents a possible extension of single-bit to multibit modulation while still maintaining the sliding-mode operation.

A delta-sigma modulator for a 1-bit digital switching amplifier

A seventh-order single-loop single-bit delta-sigma modulator for a 1-bit digital audio switching amplifier is presented. To achieve high SNR and ensure the modulator stability for a large input range, the positions of the modulator loop filter poles and zeros are optimized, and a feedback comparator is used. A test chip was fabricated in a 0.35-/spl mu/m CMOS process with optional 5-V transistors. The modulator achieves an SNR of 111 dB and 0.0015-% THD+N over the audio band. The normalized maximum allowable input range is 0.89. There are two modulators on one chip, one for each left and right audio channel. The isolation between both channels is over 135 dB. The chip area is 12.6 mm/sup 2/ and it draws 60 mA from a 5-V supply.

Low-distortion bandpass - modulator for wireless radio receivers

A low-distortion bandpass sigma-delta modulator is proposed. It was found that the key to improving linearity is to add a feedforward signal path in a double-delay resonator bandpass structure. The proposed technique improves the tonal behaviour even at low oversampling ratio and can be applied for any order of modulator. Based on the proposed architecture, a fourth-order single-bit sigma-delta modulator can achieve a dynamic range of 84 dB and a spurious free dynamic range of 98 dB at 10.71 MHz with a signal bandwidth of 200 kHz, making it ideal for a narrowband IF-sampled wireless receiver designed for compliance with GSM/GPRS standards.

Limit cycles and pattern noise in single-stage single-bit delta-sigma modulators

Pattern noise in single-bit delta-sigma modulators remains a phenomenon, which is not yet fully understood. To gain more insight into this problem, we have utilized state-space matrices to describe single-stage delta-sigma modulators operated under the condition of a constant input signal. We then established a procedure for characterizing and validating potential limit cycles. This enabled us to carry out an exhaustive search for cyclic sequences up to a length of 40 clock periods. Longer limit cycles have been found by means of an empirical, computationally more efficient random search method. This search algorithm has been applied to ideal and nonideal systems: By revealing power and frequency distribution of the tonal patterns, the numerical results yield a realistic estimate of the spurious free dynamic range. We also found that the majority of the potential limit cycles in an analog implementation can be eliminated by naturally occurring thermal noise. To be effective, the equivalent noise power of this natural dither signal must be on the order of the in-band quantization noise power of the modulator.

Structure of round-off noise in single-bit second-order sigma-delta modulators with zero input

Single-bit sigma-delta modulators are used for A-D conversion in a wide variety of systems. Analysis of first-order systems has made much progress, but the analysis of second-order systems is conventionally based on an approximate white-noise model of round-off noise. The present paper applies a new method of analysing second-order systems. It shows that, with zero input, the behaviour for each sample is equivalent to a two-dimensional discontinuous mapping Phi . It derives an invariant form under Phi and describes some of its properties. The motivation is the suggestion that the invariant form is a useful approximation to the probability distribution of round-off noise.

The basis and architecture for the reduction of tones in a sigma-delta DAC

A basis and architecture for a digital-to-analog conversion (DAC) technique that allows a significant, if not complete, reduction of the in-band tones found in single-bit sigma-delta modulators, while easing the component matching requirements compared to conventional multibit architectures, is presented. The architecture uses a combination of coarse and fine quantization levels, which resolves the input data at a rate that is sufficient to keep tones, caused by DC inputs, from occurring in the signal bandwidth. Although a DAC is discussed, it is noted that an analog-to-digital converter (ADC) has similar characteristics. Observations and additional comments relating to the time domain point of view of a sigma-delta converter are offered.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An empirical study of high-order single-bit delta-sigma modulators

Computer simulations are used to determine the stability limits of single-bit delta-sigma modulators up to order 8. It is found that none of the existing criteria for stability are adequate for design. Plots of the maximum signal-to-noise ratio (SNR) achievable with a given modulator order and oversampling ratio (OSR) are presented. These graphs can be used to determine the modulator order and OSR required to achieve a given SNR or to check the tightness of (as yet unavailable) theoretical bounds.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>