Single Bit-flips Research Articles

Saca-FI: A microarchitecture-level fault injection framework for reliability analysis of systolic array based CNN accelerator

As convolutional neural network CNN accelerators are being adopted in emerging safety-critical areas, their reliability becomes prominent. The systolic array is widely used as the major processing structure in CNN accelerators, so its reliability features need to be comprehensively explored. In this work, we develop a microarchitecture-level fault injection framework, saca-FI, to analyze the reliability of systolic array based CNN accelerators. It is able to investigate various vulnerability sources (e.g., single-bit flips, multi-bit flips, stuck-at faults, multiple faults) and at different levels (e.g., model layer and storage locations). Based on saca-FI, we evaluate the resilience of several commonly used networks, and observe several important architecture-level reliability characteristics. We then propose two opportunistic protections to demonstrate the usage of saca-FI in designing energy-efficient error protection mechanisms.

Characterizing a Neutron-Induced Fault Model for Deep Neural Networks

The reliability evaluation of Deep Neural Networks (DNNs) executed on Graphic Processing Units (GPUs) is a challenging problem since the hardware architecture is highly complex and the software frameworks are composed of many layers of abstraction. While software-level fault injection is a common and fast way to evaluate the reliability of complex applications, it may produce unrealistic results since it has limited access to the hardware resources and the adopted fault models may be too naive (i.e., single and double bit flip). Contrarily, physical fault injection with neutron beam provides realistic error rates but lacks fault propagation visibility. This paper proposes a characterization of the DNN fault model combining both neutron beam experiments and fault injection at software level. We exposed GPUs running General Matrix Multiplication (GEMM) and DNNs to beam neutrons to measure their error rate. On DNNs, we observe that the percentage of critical errors can be up to 61%, and show that ECC is ineffective in reducing critical errors. We then performed a complementary software-level fault injection, using fault models derived from RTL simulations. Our results show that by injecting complex fault models, the YOLOv3 misdetection rate is validated to be very close to the rate measured with beam experiments, which is 8.66× higher than the one measured with fault injection using only single-bit flips.

Evaluating and Mitigating Neutrons Effects on COTS EdgeAI Accelerators

EdgeAI is an emerging artificial intelligence (AI) accelerator technology, which is capable of delivering improved AI performance at both a lower cost and a lower power level. With the aim of implementation in large quantities and in safety-critical environments, it is imperative to understand how single-event effects (SEEs) affect the reliability of this new family of devices and to propose efficient hardening solutions. Through neutron beam experiments and fault-injection analysis of a commercial-off-the-shelf (COTS) EdgeAI device, we are able to identify the device's SEE failure-modes, separate the error rate contributions of the device's different resources, and characterize the device's SEE reliability. During this analysis, we discovered that the vast majority of single-bit flips have no appreciable effect on the output. After this analysis, we propose a hardening solution that implements triple-modular redundancy (TMR) in the device without changing its physical architecture. We experimentally validate this solution and show that we are able to correct 96% of the misclassifications (critical errors) with nearly zero overhead.

An Empirical Study of the Impact of Single and Multiple Bit-Flip Errors in Programs

Recent studies have shown that technology and voltage scaling are expected to increase the likelihood that particle-induced soft errors manifest as multiple-bit errors. This raises concerns about the validity of using single bit-flips in fault injection experiments aiming to assess the program-level impact of soft errors. The goal of this article is to investigate whether multiple-bit errors could cause a higher percentage of silent data corruptions (SDCs) compared to single-bit errors. Based on 2700 fault injection campaigns with 15 benchmark programs, featuring a total of 27 million experiments, our results show that single-bit errors in most cases either yield a higher percentage of SDCs compared to multiple-bit errors or yield SDC results that are very close to the ones obtained for the multiple-bit errors. Further, we find that only around 2 percent of the multiple-bit campaigns resulted in an SDC percentage that was more than 5 percentage points higher than that obtained for the corresponding single-bit campaigns. For most of these campaigns, the highest percentage of SDCs was obtained by flipping at most 3 bits. Based on our results, we also propose four techniques for error space pruning to avoid injection of multiple-bit errors that are either unlikely or infeasible to cause SDCs.

Electron-Induced Upsets and Stuck Bits in SDRAMs in the Jovian Environment

This study investigates the response of synchronous dynamic random access memories to energetic electrons and especially the possibility of electrons to cause stuck bits in these memories. Three different memories with different node sizes (63, 72, and 110 nm) were tested. Electrons with energies between 6 and 200 MeV were used at RADiation Effects Facility (RADEF) in Jyväskylä, Finland, and at Very energetic Electron facility for Space Planetary Exploration missions in harsh Radiative environments (VESPER) in The European Organization for Nuclear Research (CERN), Switzerland. Photon irradiation was also performed in Jyväskylä. In these irradiation tests, stuck bits originating from electron-induced single-event effects (SEEs) were found, as well as single bit-flips from single electrons. To the best knowledge of the authors, this is the first time that stuck bits from single-electron events have been reported in the literature. It is argued in the article that the single-event bit-flips and stuck bits are caused by the same damage mechanism, which would be large displacement damage clusters, and that the two different fault modes represent different amounts of damage to the memory cell. After a large particle fluence, a rapid increase in the error rate was observed, originating from the accumulation of smaller displacement damage clusters in the memory cells. The 110-nm memory was a candidate component to fly on the European Space Agency (ESA) JUpiter ICy moons Explorer (JUICE) mission, so the SEE cross section as a function of electron energy was compared to the expected electron environment encountered by JUICE to estimate the error rates during the mission.

Efficient Detection for Malicious and Random Errors in Additive Encrypted Computation

Although data confidentiality is the primary security objective in additive encrypted computation applications, such as the aggregation of encrypted votes in electronic elections, ensuring the trustworthiness of data is equally important. And yet, integrity protections are generally orthogonal to additive homomorphic encryption, which enables efficient encrypted computation, due to the inherent malleability of homomorphic ciphertexts. Since additive homomorphic schemes are founded on modular arithmetic, our framework extends residue numbering to support fast modular reductions and homomorphic syndromes for detecting random errors inside homomorphic ALUs and data memories. In addition, our methodology detects malicious modifications of memory data, using keyed syndromes and block cipher-based integrity trees, which allow preserving the homomorphism of ALU operations, while enforcing non-malleability of memory data. Compared to traditional memory integrity protections, our tree-based syndrome generation and updating is parallelizable for increased efficiency, while requiring a small Trusted Computing Base for secret key storage and block cipher operations. Our evaluation shows more than 99.999 percent detection rate for random ALUs errors, as well as 100 percent detection rate of single bit-flips and clustered multiple bit upsets, for a runtime overhead between 1.2 and 5.5 percent, and a small area penalty.