Effect Of Simultaneous Switching Noise Research Articles

Suppression of Simultaneous Switching Noise Using Embedded Capacitor Method in High-Speed Systems

Gbps signals are commonly used in modern high-speed IO designs. These systems require a high level of signal accuracy. However, these signals can cause current fluctuations at high frequencies due to parasitic inductance on the package and board, leading to significant changes in supply voltage. DDRX interfaces that transmit data up to 4.8 Gbps induce simultaneous switching noise (SSN) in the voltage regulator module (VRM). One of the adverse effects of SSN is timing jitter, also known as power supply-induced jitter. The amount of SSN is directly proportional to the number of signals on a parallel bus. Discrete capacitors may not be effective in reducing SSN impact when data is transmitted at high speeds. The current approach used to predict and evaluate errors in SSNs relies on the designer's expertise, which requires accurate estimates of packaging parasitic. In this paper, a practical approach to lessen SSN is presented through the use of embedded capacitors placed between planes and optimizing discrete capacitors by connecting them in a way that measures the impact of supply noise on the I/O transistor circuit performance at the DDRX interface. Two boards were designed, evaluated, and subsequently compared their results.

Simultaneous Switching Noise Effects in Graphene-Based Power Distribution Networks

The simultaneous switching noise (SSN) effects in graphene nanoribbon field effect transistor (GNRFET) based ternary circuits are presented in this study. The performance in terms of SSN induced peak noise and propagation delay on power and ground rails are investigated in multilayer graphene nanoribbon (MLGNR) bundled power interconnects using Hewlett simulation program with integrated circuit emphasis (HSPICE) simulator. Furthermore, these investigations are compared to the copper (Cu) and multiwalled carbon nanotubes (MWCNT) based power interconnects. From the results, it is noticed that the proposed MLGNR interconnects shows performance improvements up to 74.9% and 33.8% over the Cu and MWCNT interconnects. Moreover, the SSN peak noise and delay are investigated for different interconnect lengths from 200 μm to 500 μm. It is observed that the SSN noise on power and ground rail is reduced and propagation delay is increased as interconnect length is increased.

Analysis, Modeling and Reduction of the SSN Effects on an Integrated Circuit

Nowadays, microcontrollers are massively used on the market for a wide range of applications. One of their functionalities is the high-speed communications that are at the origin of the SSN (Simultaneous Switching Noise) effect. Today, more than ever, it becomes crucial to improve the robustness of the microcontroller against the SSN effect on purpose to acquire a comparative advantage on the market or simply to ensure the good microcontroller behavior. This article details the SSN origin and problematic as the effects on power supply integrity. Then it introduces a methodology of modeling and correlation of a complete system — a die with its associate package and PCB — in order to study the SSN effect as well as all influencing parameters only by simulations. This modeling method can also be applied to anticipate future microcontroller behavior regarding the SSN effect. Finally, an overview of design rules found is described.

Constant Voltage-Based Power Delivery Scheme for 3-D ICs and Interposers

Advances in 3-D integrated circuit (3-DIC) technology have allowed for advantages in integration, system speed, and power consumption for digital systems. In systems operating at very high data rates with large data width, the effect of simultaneous switching noise (SSN) can, however, drastically affect system performance. Therefore, the effect of SSN in the power delivery network (PDN) design of a through silicon via (TSV)-based 3-D stack has been investigated in this paper, and eye diagrams have been simulated in each level of the stack to analyze power supply noise and transition jitter. Using a novel PDN design concept based on constant voltage power transmission lines, it is shown that this new PDN design can significantly improve signal quality in a 3-DIC application. The 3-D system considered here consists of a PCB, an interposer, and three IC dies. Each IC contains a TSV layer, PDN, and digital logic.

Parasitic Modeling and Analysis for a 1-Gb/s CMOS Laser Driver

A differential laser driver (LD) operating at 1 Gb/s has been designed and tested using NSC 0.35-/spl mu/m CMOS technology. The effect of simultaneous switching noise caused by packaging parasitic was addressed and the parasitic model was developed to predict the exact behavior of circuit performance. With the developed parasitic model, the LD simulation results showed the degradation of the output signal. Thus, the effectiveness of the decoupling capacitor was suggested and investigated through the LD design. However, the test results did not match with the expected results due to the parasitic in the input and output nodes. Hence, the back-annotated analysis was performed with the developed parasitic models and the simulated output of the LD matched with that of the tested results.

Capacitor placement for switching noise reduction using genetic algorithms and distributed computing

This work investigates capacitor placement on a printed circuit board (PCB) to reduce the effect of simultaneous switching noise as a genetic algorithm (GA) search problem. The solution process makes use of distributed computing resources available on a local area network in order to solve larger problems more efficiently. The objective is to determine the number of added capacitors with minimum cost, and their position on the PCB, while keeping the maximum voltage deviation within some specified noise margin. The presence of capacitors at the selected positions is represented by a stream of zeros and ones, which is interpreted as a genotype. At each generation, the GA assesses the fitness function of a population of genotypes using linear transient circuit analysis, which involves a single matrix inversion, by determining the maximum voltage dip given the capacitor locations. For large systems, the fitness calculations are divided among several processors according to a simple distributed computing algorithm.

A simple finite-difference frequency-domain (FDFD) algorithm for analysis of switching noise in printed circuit boards and packages

Simultaneous switching noise (SSN) compromises the integrity of the power distribution structure on multilayer printed circuit boards (PCB). Several methods have been used to investigate SSN. These methods ranged from simple lumped circuit models to full-wave (dynamic) three-dimensional Maxwell equations simulators. In this work, we present an efficient and simple finite-difference frequency-domain (FDFD) based algorithm that can simulate, with high accuracy, the capacity of a PCB board to introduce SSN. The FDFD code developed here also allows for simulation of real-world decoupling capacitors that are typically used to mitigate SSN effects at sub 1 GHz frequencies. Furthermore, the algorithm is capable of including lumped circuit elements having user-specified complex impedance. Numerical results are presented for several test boards and packages, with and without decoupling capacitors. Validation of the FDFD code is demonstrated through comparison with other algorithms and laboratory measurements.

Effects of simultaneous switching noise on the tapered buffer design

Complementary metal-oxide-semiconductor (CMOS) output buffers, comprised of a series of tapered inverters, are used to drive large off-chip capacitances. The ratio of the size of transistors between two consecutive stages is the buffer taper factor. With higher frequency of operation and simultaneous switching of the output drivers, the parasitic inductance present at the pin-pad-package interface results in significant switching noise on the power lines. A comprehensive analysis and estimate of simultaneous switching noise (SSN) including the velocity saturation effects seen in the submicron transistors during the switching of output drivers is presented. The effect of SSN on the overall buffer propagation delay and transition time is discussed. The presence of SSN results in an increase in the optimum taper factor between inverter stages for a given capacitive load. Beyond a critical value, the output transition time of a tapered buffer increases with reducing taper factor due to SSN. SSN can be reduced by skewing the switching of output buffers, SPICE simulation results show that skewing buffer switching with additional inverter stages reduces SSN and increases buffer propagation delay.

Computation of switching noise in printed circuit boards

Simultaneous switching noise (SSN) is a phenomenon with adverse and severe effects when a large number of high speed chip drivers switch simultaneously causing a large amount of current to be injected into the power distribution grid. The effects of SSN are manifested in a variety of transient and permanent system malfunctions including the appearance of undesirable glitches on what should otherwise be quiet signal lines and the flipping of state bits in registers and memories. Current approaches for dealing with SSN are largely ad hoc, relying primarily on the ability of expert designers to postulate worst-case scenarios for the occurrence of SSN-related errors and to analyze these scenarios using pessimistic estimates of packaging parasitics. This paper takes a first step toward evolving a systematic methodology for modeling and analysis of SSN in printed circuit boards (PCB's). The presented methodology adopts a combination of macro- and micro-models which allow for a system level treatment of the problem without losing the necessary detailed descriptions of the power/ground planes, the signal traces and the vertical interconnections through vias or plated holes. This approach has been applied to a variety of PCB structures and has allowed for an effective characterization of switching noise and a comprehensive understanding of its effects on PCB performance.