Simultaneous Switching Noise Analysis Research Articles

Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and $\mu$ TSVs

In this article, a power delivery network (PDN) modeling framework for backside-PDN configurations is presented. A backside-PDN configuration contains dense microthrough silicon vias ( $\mu $ TSVs) and power/ground metal stack on the backside of the die. This approach separates the PDN from a conventional signaling network of the back-end-of-the-line (BEOL) and improves power integrity and core utilization. We benchmark this technology with conventional front-side BEOL PDN configurations. Owing to the lower resistivity compared with Cu metal lines for advanced technology nodes, we use ruthenium (Ru)-based buried power rail for PDN modeling. Our analysis shows that the steady-state IR-drop reduces by more than $4\times $ in the backside-PDN configuration, and a simultaneous switching noise analysis shows a significant reduction in transient droops. The framework results are validated with a place-and-route (P&R)-based physical implementation flow. We quantify the area improvement in the actual flow and observe 25%–30% improvement in the backside-PDN configuration. From a PDN modeling framework, the PDN results follow a trend similar to the ones obtained from the block-level P&R of the given configurations. Moreover, we investigate the impacts of package-to-die interconnect pitch, metal–insulator–metal cap density, and input pulse on the PDN performance. In addition, we perform thermal modeling to analyze the thermal implications of the backside-PDN configuration. From a thermal modeling perspective, there is negligible influence from a dielectric bonding layer in the backside-PDN configuration.

Analysis of Simultaneous Switching Noise and IR-Drop in Side-Contact Multilayer Graphene Nanoribbon Power Distribution Network

The work in this paper presents the analyses of temperature-dependent simultaneous switching noise (SSN) and IR-Drop in multilayer graphene nanoribbon (MLGNR) power interconnects for 16[Formula: see text]nm ITRS technology node. A [Formula: see text] standard cell-based integrated circuit is designed to analyze the SSN and IR-Drop using the proposed temperature-dependent model of MLGNR and Cu interconnect for 10[Formula: see text][Formula: see text]m interconnect length at temperatures (233[Formula: see text]K, 300[Formula: see text]K and 378[Formula: see text]K). Our analysis shows that MLGNR exhibits ([Formula: see text]–[Formula: see text]) less SSN and ([Formula: see text]–[Formula: see text]) less IR-Drop as compared with traditional Cu-based power interconnects. Our analysis also shows that the average percentage of reduction in peak SSN is 52–32% (at 233[Formula: see text]K), 53–32% (at 300[Formula: see text]K) and 52–30% (at 378[Formula: see text]K) less in MLGNR compared with traditional Cu-based power interconnect and the average percentage of reduction in peak IR-Drop in MLGNR is 54–31% (at 233[Formula: see text]K), 57–29% (at 300[Formula: see text]K) and 57–26% (at 378[Formula: see text]K) less than that of Cu-based power interconnects.

Simultaneous switching noise analysis: The relation between bus layout, coding and switching patterns

Simultaneous switching noise analysis: The relation between bus layout, coding and switching patterns

Application of Asymptotic Waveform Evaluation to Eigenmode Expansion Method for Analysis of Simultaneous Switching Noise in Printed Circuit Boards (PCBs)

In this paper, the asymptotic waveform evaluation (AWE) technique is first applied to the conventional eigenmode expansion method for characterizing a power/ground (P/G) plane pair and analyzing the simultaneous switching noise on such plane pairs for printed circuit boards or multichip modules. The application of AWE avoids a large number of iterations in computing the impedance frequency response of a P/G plane pair structure and greatly reduces the computation time. Meanwhile, to obtain an accurate solution in an entire frequency range, we employ the complex frequency hopping technique which can help select multiple expansion points. In addition, the proposed approach can also be used to characterize the P/G plane pair structures with irregular shapes. Three examples demonstrate its high efficiency and good accuracy

Simultaneous switching noise analysis using application specific device modeling

In this paper, we introduce an application-specific device modeling methodology to develop simple device model that accurately tracks the actual device I-V characteristics in relevant but bounded operating regions. We have specifically used a simple MOSFET model to precisely analyze the switching noises generated on a chip due to simultaneous driving of chip output pads by bulky buffer gates. Previous works in analytical modeling of simultaneous switching noises employed long-channel and /spl alpha/-power law transistor models; however, these models led to complex circuit equations that on truncation caused poor matching between manual analysis and actual simulation results. Also, in order to retain the simplicity of manual analysis, previous researchers ignored the parasitic capacitances of the bonding pads. This paper demonstrates that by using a simple application-specific transistor model, circuit equations can be solved precisely without requiring any gross approximations or model truncations, even when the inductance effects of bonding wires are simultaneously considered along with parasitic capacitances of the output pads. The analytical results derived in this paper tally with HSPICE simulation values within 3% deviations.

Simultaneous switching noise analysis and low-bounce buffer design

An accurate equation to estimate simultaneous switching noise (SSN) created by CMOS output buffers is proposed. This analytic equation includes the carrier velocity saturation effects of a short-channel MOS transistor. Simulation results show that the proposed closed-form equation estimates the SSN precisely and the error is below 10% as compared with HSPICE simulation results. Design procedures of a low-bounce tapered buffer which take SSN into consideration are also proposed. Several output buffer design examples are demonstrated to show the significant improvement of the low-bounce buffer design. A test chip of the output buffer is implemented to operate at 400 MHz and the measurement results match the design specifications.

New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design

A new simple but accurate simultaneous-switching-noise (SSN) model for complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) package design was developed. Since the model is based on the sub-micron metal-oxide-semiconductor (MOS) device model, it can predict the SSN for today's sub-micron-based very large scale integration (VLSI) circuits. In order to derive the SSN model, the ground path current is determined by taking into account all the circuit components such as the transistor resistance, lead inductance, load capacitance, and oscillation frequency of the noise signal. Since the current slew rate is not constant during the device switching, a rigorous analysis to determine the current slew rate was performed. Then a new simple but accurate closed-form SSN model was developed by accurately determining current slew rate for SSN with the alpha-power-law of a sub-micron transistor drain current. The derived SSN model implicitly includes all the critical circuit performance and package parameters. The model is verified with the general-purpose circuit simulator, HSPICE. The model shows an excellent agreement with simulation even in the worst case (i.e., within a 10% margin of error but normally within a 5% margin of error). A package design methodology is presented by using the developed model.

S-parameter based technique for simultaneous switching noise analysis in electronic packages

A method based on S-parameters is developed for the analysis of simultaneous switching noise (SSN) in electronic packages. A two-port Z matrix of the package pin/trace, and the coupling between the pins/traces are modeled by analytical equations. SSN is analyzed as a function of the number of switching drivers and switching time. Frequency domain measurements are performed to demonstrate the accuracy of the model. The modeling methodology is applied to both leaded and area array packages.

Computation of switching noise in printed circuit boards

Simultaneous switching noise (SSN) is a phenomenon with adverse and severe effects when a large number of high speed chip drivers switch simultaneously causing a large amount of current to be injected into the power distribution grid. The effects of SSN are manifested in a variety of transient and permanent system malfunctions including the appearance of undesirable glitches on what should otherwise be quiet signal lines and the flipping of state bits in registers and memories. Current approaches for dealing with SSN are largely ad hoc, relying primarily on the ability of expert designers to postulate worst-case scenarios for the occurrence of SSN-related errors and to analyze these scenarios using pessimistic estimates of packaging parasitics. This paper takes a first step toward evolving a systematic methodology for modeling and analysis of SSN in printed circuit boards (PCB's). The presented methodology adopts a combination of macro- and micro-models which allow for a system level treatment of the problem without losing the necessary detailed descriptions of the power/ground planes, the signal traces and the vertical interconnections through vias or plated holes. This approach has been applied to a variety of PCB structures and has allowed for an effective characterization of switching noise and a comprehensive understanding of its effects on PCB performance.

A package analysis tool based on a method of moments surface formulation

A package analysis tool that is based on a method of moments analysis and surface formulation is described. The surface formulation replaces ideal conductors by electric currents on their surfaces, while electric and magnetic currents are used for lossy conductors. These currents are then discretized using triangular linear current approximations, with the primary advantage of being able to represent arbitrary shapes. Frequency-dependent inductance and resistance are computed. The capacitance is also computed using piecewise-constant charge distributions on each triangle. The current and charge distributions are compatible, and therefore transmission line modeling can be done accurately. The algorithm allows use of the tool for both transmission line and discontinuity modeling, as well as analysis of simultaneous switching noise. The tool has a graphical pre- and postprocessor, which allows analysis of highly irregular structures, are found in most practical packaging configurations. An analysis of simultaneous switching noise for a 304-lead, six-layer single-chip module is presented as an example.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>