Simultaneous Memory Accesses Research Articles

Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time Systems

Modern real-time embedded systems are equipped with multi-core processors to execute computationally intensive tasks. In multi-core architecture, last-level cache memory is shared by cores. The shared cache becomes a non-deterministic resource, which affects the independent execution of real-time tasks. We propose a solution to remedy a variation in execution time when interference happens in a shared cache. Current solutions have relied on memory scheduling approaches that avoid concurrent memory access to guarantee deterministic execution time. However, these methods required complex analysis to accurately estimate the worst-case execution time and to schedule tasks in an overly conservative manner. Unlike existing works, the proposed method prevents simultaneous memory access using the side effect of memory barriers rather than the complicated analysis. A memory barrier is inserted based on a simple code analysis that is performed in units of basic blocks using the LLVM compiler. The proposed method not only does not require the modification of the operating system or task execution flow but also relatively shows fast analysis time. Experimental results show that the proposed basic block-based memory barrier insertion method can reduce the variation in execution time by up to 80% when interference occurs.

Thread scheduling and memory coalescing for dynamic vectorization of SPMD workloads

We propose a new thread synchronization heuristic called Min-SP/PC.Min-SP/PC handles function calls better than previous algorithms.Many instructions in SPMD programs are identical across threads.Many memory accesses are either uniform or affine across threads. Simultaneous Multi-Threading (SMT) is a hardware model in which different threads share the same processing unit. This model is a compromise between high parallelism and low hardware cost. Minimal Multi-Threading (MMT) is one architecture recently proposed that shares instruction decoding and execution between threads running the same program in an SMT processor, thereby generalizing the approach followed by Graphics Processing Units to general-purpose processors. In this paper we propose new ways to expose redundancies in the MMT execution model. First, we propose and evaluate a new thread reconvergence heuristic that handles function calls better than previous approaches. Our heuristic only inspects the program counter and the stack frame to reconverge threads; hence, it is amenable to efficient and inexpensive hardware implementation. Second, we demonstrate that this heuristic is able to reveal the existence of substantial regularity in inter-thread memory access patterns. We validate our results on data-parallel applications from the PARSEC and SPLASH suites. Our new reconvergence heuristic increases the throughput of our MMT model by 7%, when compared to a previous, and substantially more complex approach, due to Long et al. Moreover, it gives us an effective way to increase regularity in memory accesses. We have observed that over 70% of simultaneous memory accesses are either the same for all the threads, or are affine expressions of the thread identifier. This observation motivates the design of newly proposed hardware that benefits from regularity in inter-thread memory accesses.

A reordered first fit algorithm based novel storage scheme for parallel turbo decoder

In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural order in storage, our scheme requires 25 more memory blocks but allows a simpler configuration for variable sizes of code lengths that can be implemented on-chip. Experiment shows that for a moderate to high decoding throughput (40∼100 Mbps), the hardware cost is still affordable for 3GPP’s (3rd generation partnership project) interleaver.

Minimizing the required memory bandwidth in VLSI system realizations

In this paper, we present the problem of storage bandwidth optimization (SBO) in VLSI system realizations. Our goal is to minimize the required memory bandwidth within the given cycle budget by adding ordering constraints to the flow graph. This allows the subsequent memory allocation and assignment tasks to come up with a cheaper memory architecture with less memories and memory ports. The importance and the effect of SBO is shown on realistic examples both in the video and asynchronous transfer-mode (ATM) domains. We show that it is important to take into account which data is being accessed in parallel, instead of only considering the number of simultaneous memory accesses. Our problem formulation leads to the optimization of a conflict (hyper) graph. For the target domain of ATM, only flat graphs without loops have to be treated. For this subproblem, a prototype tool has been implemented to demonstrate the feasibility of automating this important system design step.

A conflict free memory access in parallel image reconstruction

The paper addresses a conflict free access to the memory in parallel image reconstruction. A simultaneous memory access is discussed in terms of the forms of parallelism specific to image reconstruction. Two types of mapping of the projection space onto the image space are defined and their influence on a simultaneous memory access is analysed. Finally, two approaches allowing to attain a conflict free memory access are proposed: parallelism degree restriction and memory access synchronization.

The M7 - A High Speed Digital Processor for Second Level Trigger Selections

A digital processor is described which reconstructs mass and momentum as a second level trigger selection. The processor is a five-address, microprogrammed, pipelined, ECL machine with simultaneous memory access to four operands which load two parallel multipliers and an ALU. Source data modules are extensions of the processor.

On-line Computer Control of a Formant Synthesizer

A solid-state formant synthesizer has been constructed and interfaced to a digital computer. The computer, a DDP-24, has a 12K memory, and a 5-μsec cycle time. The computer-synthesizer combination permits on-line, real-time synthesis of speech under program control. The synthesizer has a number of useful features: optional serial or parallel operation; high-accuracy, wide-range control of three formant frequencies (±0.50% over a 20:1 range for F1); individual control of three formant bandwidths; unusual fidelity in spectral representation; and exceptionally low noise level. Amplitude controls are accomplished by linear multipliers with 60-dB range, hence frequency responses may be run with sine waves. Programming of the system is especially simple. Controls are normalized so that formant frequencies, bandwidths, and amplitudes at resonance are specified independently and without interaction. A data scan is accomplished under program control with only three instructions additional to those for computation. Alternatively, most of the data outputting can be done through a simultaneous memory access channel, with automatic program interruption for periodic servicing of the channel. Synthetic speech produced by the computer-controlled synthesizer is demonstrated.