Simulation Of Single Electron Transistor Research Articles

A New Tool for Simulation of Single Electron Transistor based Microprocessor Using Vector File

Background: A microprocessor is a general-purpose device, which works on the user defined instructions. The design of next generation microprocessors demands high speed, high density and low power requirements that can be attained by prominent device like Single Electron Transistor (SET). Methods: Based on realizable SET parameters at room temperature and 800 mV operating voltage; an 8-bit SET based microprocessor is designed and simulated using Cadence Virtuoso environment. The simulation of the microprocessor requires complex stimuli to verify the design for multiple instructions. Conventionally, the simulation is performed by applying individual signal source to each signal. However, that is not optimum and viable for microprocessor designs. Results: The Cadence Spectre simulator has a facility to simulate the design using vector file, which combines multiple signal sources in a text file. In addition, writing vector file manually is complex and erroneous. Conclusion: To overcome the problem, a tool is designed and developed that generates a vector file for user selected instructions and parameters. The usage of vector file makes the simulation straightforward and accurate. This paper describes the design of a tool for vector file generation.

Design and Simulation of Single Electron Transistor based SRAM and its Memory Controller at Room Temperature

Heterogeneous 3D integration of single electron transistor (SET) circuits with CMOS based circuits is achieved by stacking a SET layer above CMOS IC. Low power and delay efficient circuits can be designed using SET. In this paper, we have designed and simulated 6T SRAM array operating at room temperature and at CMOS comparable voltage. Peripheral circuit like sense amplifier, decoder, write circuit and pre-charge circuit using SET have been designed for optimum performance. The stability of 6T SRAM cell is verified using N-curve method. The designed SET based 8 x 8 bit SRAM is 99.54 % power efficient, 92.19 % faster in write access time and 78.58 % faster in read access time compared to 16 nm CMOS based SRAM. The SRAM is designed to work at CMOS comparable voltage of 800 mV, which can be scaled up to 20 mV with better efficiency. The designed SRAM is tested and verified for variation in process, voltage and temperature. The maximum frequency of operation for the designed SET based SRAM with memory controller is 4 GHz.

Modeling and Simulation of Single-Electron Transistor (SET) with Aluminum Island Using Neural Network

Abstract SET is important in the field of nanoelectronics since a decade. This paper presents electrical characteristic of Single-Electron Transistor (SET) with Aluminum Island using Neural Network. The I-V characteristic of the Single-Electron Transistor (SET) is predicted according to different parameters (VG, T, VD, C, and R). The simulation process is based on analytical transistor model and neural network transistor model. Single Electron Transistor (SET) is the simplest device in which the effect of Coulomb blockade can be observed.

Analysis and simulation of Single Electron Transistor as an analogue frequency doubler

Performance of Single Electron Transistors as analogue frequency doublers is evaluated by analysis and HSPICE simulations. First, a macro model is selected which represents the device characteristics adequately. The model parameters are determined for different devices reported in the literature, based on their DC characteristics. Adding terminal capacitances to the device model, the small-signal AC performance of the transistors are then simulated. It is observed that the selected devices can operate up to GHz frequencies. Then large signal theory of operation of a common source doubler with resistive loading is developed based on the selected model. Simulations for resistor and transistor loaded circuits with HSPICE are also presented. There is good agreement between the simulation results and those from the closed form analytical expressions. The device analysis and simulations indicate that the device can be used as a doubler in its Coulomb blockade region of operation. Conversion gain (loss) of −13 dB, and harmonic distortion of 12% can be expected.

Modeling and simulation of single electron transistor with master equation approach

In this paper, we discuss modeling and simulation of single dot Single Electron Transistor (SET) using master equation approximation. For SET modeling and simulation, master equation method treats the electron tunneling and its transition probabilistically. The probability of electron tunneling is used to determine the current density in accordance with selected input parameters. The calculation results show fairly accurate electrical characteristics of SET as compared with experimental data. Staircase pattern from I-V are clearly obtained as the main role of coulomb blockade effect in SET system. We also extend our calculation by introduce some additional parameters such as; the effect of working temperature, gate voltage dependent, and the influence of resistance to the device characteristic. We found that increasing operational temperature will promote higher current density, both in forward and reverse bias region. In the case of using single dot with 30 nm × 80 nm × 125 nm dimension, coulomb blockade effect could be reduced by applying gate voltage higher than 3V and setting drain resistance higher than source's. Our studies show an alternative approach in modeling and simulation of electronic devices and could be potential for development of novel nanoelectronic devices.

A modified macro model approach for SPICE based simulation of single electron transistor

A new macro model of single electron transistor (SET) for SPICE based simulation of SET circuits is proposed. Two voltage controlled current sources and some scaling factors are incorporated in the existing model to derive our model. The V---I characteristics of the proposed SET is promising enough to be used as the basic element for designing circuits based on SETs. A comparison with the previous models establishes the fact that our model efficiently removes the drawbacks of the existing models. Our model also agrees well with the results obtained from popular SIMON simulator. To verify the accuracy, we have designed a SET inverter cell and investigated its characteristics. The work includes the effect of the parameters on the noise margin and voltage transfer characteristics of the inverter circuit. Further, to verify the applicability, a multi peak negative differential resistance circuit based on the proposed model is designed and simulated.

A New SPICE Macro-Model for Simulation of Single Electron Circuits

In this paper we have proposed a new and more accurate macro-model for simulation of single electron transistors (SETs). Furthermore, this model includes the ability of electron tunneling time calculation. In our proposed model, we have modified the previous models and applied some basic corrections to their formulas. In addition to achievement of more accuracy, we have added a switched capacitor circuit, as a quantizer, to evaluate the time of electron tunneling through the barrier. We used HSPICE for high-speed simulation and observed that our macro-model gives more accurate results than of the other models when compare with SIMON 2.0. This model is completely applicable for calculating the delay time of complicated circuits.

Modeling and simulation of single-electron transistors

Single-electron transistor (SET) can offer lower power consumption and faster operating speed in the era of nanotechnology. It operates in single electronics regime where only one electron can tunnel from source to drain via island. Thus single electron tunneling is the phenomena that describe the principle of SET. Owing to the stochastic nature of the tunneling event, a tunneling electron is considered as a discrete charge. To simulate the SET, Monte Carlo method is used due to its reasonable accuracy in the single electronics simulation. A model is described and used to study the electronic properties of SET. Monte Carlo method follows the tunneling path of a representative number of electrons and it can gives a clear picture of the inner work of the single electron circuits.

Consideration of the “island” background charge in single-electron transistor simulation

Three approximations of the “island” background charge are described within the proposed 2D numerical model of the metal single-electron transistor. These approximations fit the experimental data well when calculating I–V characteristics of single-electron transistors according to the model developed in many cases. The validity of these approximations is exemplified by specific calculations of I–V characteristics.

Electron Transport in Nanocrystalline Si Based Single Electron Transistors

Electron transport has been studied by measurement and simulation of single electron transistors based on nanocrystalline silicon (nc-Si). Nanocrystalline silicon is formed in the gas phase of the SiH4 plasma cell by the coalescence of radicals. Digital chemical vapor deposition [CVD] technique using pulsed gas in the plasma is effective to obtain highly uniform Si quantum dots with an average size of 8 nm and dispersion of 1 nm. Single electron transistors have been successfully fabricated by deposition of nc-Si on top of heavily doped silicon nanoelectrodes with a gap of 15 nm which allows the study of electron transport through two or three nanocrystals. Coulomb blockade and Coulomb oscillations are observed in these devices at various temperatures, including room temperature. The observed Coulomb diamond structure is not as simple as in the case of metallic islands. With increasing gate voltage, the spacing between oscillation peaks decreases and the Coulomb diamonds reduce in size. These observations are explained on the basis of electron transport through a quantum dot with an energy gap between the highest occupied and the lowest unoccupied electron states. Modeling of such a system can reproduce measured electrical characteristics. The unequal spacing of gate oscillations and the reduced size of Coulomb diamonds are due to the interplay of Coulomb charging energy and the energy separation between the quantized energy levels.