Simulation Of Integrated Circuits Research Articles

A Machine Learning Approach for the Forecasting of Computing Resource Requirements in Integrated Circuit Simulation

For the iterative development of the chip, ensuring that the simulation is completed in the shortest time is critical. To meet this demand, the common practice is to reduce simulation time by providing more computing resources. However, this acceleration method has an upper limit. After reaching the upper limit, providing more CPUs can no longer shorten the simulation time, but will instead waste a lot of computing resources. Unfortunately, the recommended values of the existing commercial tools are often higher than this upper limit. To better match this limit, a machine learning optimization algorithm trained with a custom loss function is proposed. Experimental results demonstrate that the proposed algorithm is superior to commercial tools in terms of both accuracy and stability. In addition, the simulations using the resources predicted by the proposed model maintain the same simulation completion time while reducing core hour consumption by approximately 30%.

Modeling and simulation for transient thermal analyses using a voltage-in-current latency insertion method

This article presents a modeling and simulation method for transient thermal analyses of integrated circuits (ICs) using the original and voltage-in-current (VinC) latency insertion method (LIM). LIM-based algorithms are a set of fast transient simulation methods that solve electrical circuits in a leapfrog updating manner without relying on large matrix operations used in conventional Simulation Program with Integrated Circuit Emphasis (SPICE)-based methods which can significantly slow down the solution process. The conversion from the thermal to electrical model is performed first by using the analogy between heat and electrical conduction. Since electrical inductance has no thermal equivalence, a modified VinC LIM formulation is presented which removes the requirement of the insertion of fictitious inductors. Numerical examples are presented which show that the modified VinC LIM formulation outperforms the basic LIM formulation, both in terms of stability and accuracy in the transient thermal simulation of ICs.

Migrating Assertions From Dense to Discrete Time

Mixed-signal assertions need to be monitored over dense time during analog simulation because analog events are not aligned with clock boundaries in general. On the other hand, simulation of large integrated circuits regularly employs clocked approximations to accelerate the simulation of the analog content in the design. Migrating the analog assertions from the continuous setting to the discrete setting is necessary to monitor compliance in the digital–analog boundary, but such migration must ensure that assertion failures are not missed due to the loss in precision. We propose the formal basis for this migration and a methodology for choosing the granularity of the clock for an assertion in the digital setting.

A methodology for thermal simulation of interconnects enabled by model reduction with material property variation

A thermal simulation methodology is developed for interconnects enabled by a data-driven learning algorithm accounting for variations of material properties, heat sources and boundary conditions (BCs). The methodology is based on the concepts of model order reduction and domain decomposition to construct a multi-block approach. A generic block model is built to represent a group of interconnect blocks that are used to wire standard cells in the integrated circuits (ICs). The blocks in this group possess identical geometry with various metal/via routings. The data-driven model reduction method is thus applied to learn material property variations induced by different metal/via routings in the blocks, in addition to the variations of heat sources and BCs. The approach is investigated in two very different settings. It is first applied to thermal simulation of a single interconnect block with similar BCs to those in the training of the generic block. It is then implemented in multi-block thermal simulation of a FinFET IC, where the interconnect structure is partitioned into several blocks each modeled by the generic block model. Accuracy of the generic block model is examined in terms of the metal/via routings, BCs and thermal discontinuities at the block interfaces.

A Fast and Fully Parallel Analog CMOS Solver for Nonlinear PDEs

A general-purpose analog computing method is proposed to compute the continuous-time solutions of nonlinear partial differential equations (PDEs). The discrete-time difference operator in the standard finite difference time domain (FDTD) method is replaced by continuous-time delay operators that can be realized using analog all-pass filters. The resulting spatially discrete time-continuous (SDTC) update equations are realized using analog circuits which compute continuous-time solutions of the PDE with prescribed initial and boundary conditions. The proposed concept is demonstrated in simulation via an integrated circuit (IC) design of a nonlinear acoustic wave equation solver in 180 nm CMOS technology. Analog arithmetic operations (multiply, scale, and add) are realized in parallel using fully differential op-amps and analog multipliers. The proposed IC computes the PDE solution in parallel at 33 discrete spatial points and has a simulated bandwidth and power consumption of approximately 2 MHz and 3 W, respectively. The performance of the IC is simulated using foundry-supplied device models and quantified using i) the mean squared difference between the circuit simulation results and FDTD simulations, and ii) the noise to signal energy ratio. Acceptable accuracy is obtained, with error metric values varying between -7 and -30 dB for various configurations of the problem. Comparison of the custom analog IC simulations with MATLAB- and C-based FDTD code running on a modern workstation shows an expected average speedup of 205× and 140×, respectively.

On Model Order Reduction of Interconnect Circuit Network: A Fast and Accurate Method

The time cost in integrated circuit simulation is an important consideration in the design. This paper investigates the model order reduction of interconnect circuit networks to facilitate numerical analysis. A novel fast and accurate time reduced order model is proposed to simplify the interconnection network structure analysis and perform a fast simulation. The novelty of this study is the use of the power function sum to extend the approximate function to replace the original system’s state function. We give several simulations to verify the effectiveness of the algorithm. The innovation of this model is due to its use of the approximate function of power series expansion to replace the state function of the original system.

Development of Faraday rotation measurements on Keda Reconnection eXperiment (KRX) device.

The Faraday-effect based polarimeter and interferometer are developed for non-perturbation magnetic field and density measurements on the Keda Reconnection eXperiment (KRX) device. The magnetic reconnection is externally driven by a pair of parallel current plates. To design this instrument and provide an alternative way to facilitate theory-experiment comparisons via forward modeling of the diagnostics process with full plasma dynamics given by simulation, we develop a synthetic diagnostics based on 2D photonic integrated circuit simulation for magnetic reconnection on the KRX. The view-line geometry is optimized and wavelengths (1mm) of the polarimeter and interferometer are selected to ensure the sensitivity of measurement on the KRX. We have simulated magnetic reconnection on the x-line (x-z plane) with horizontal viewing and vertical viewing for line of sight measurements. It is found that the current sheet width and indicator of magnetic reconnection can be inferred directly from the dynamics of Faraday rotation even with the line-integrated character of polarimeter-interferometer diagnostics.

Formulae for Calculating the Resistance Parameters of Irregular Through-silicon Via

The through-silicon via (TSV) is a key technology in the three-dimensional integrated circuit, and the accuracy of its parasitic parameter extraction is the important factor of ensuring accuracy of the integrated circuit simulation. Due to the influence of the production process, the through-silicon via (TSV) is not a cylinder with a smooth surface and regular shape, and with an increase in the frequency and decrease in the size of the TSV, the irregular shape has more and more influence on the parameter extraction of the TSV. To extract the resistance parameters of an irregular TSV more rapidly and accurately, we studied the high surface ratio trapezoid and rough surface TSV and put forward the analytic expressions for calculating the resistance. The two analytic expressions reflect the change rule of resistance parameters along with the size and frequency variation of the TSV. The error of analytic expression was within 5% when compared with the simulation results, which fully satisfies the requirement of accuracy.

Early Stage EMS Simulation of Automotive Integrated Circuits

In the automotive industry, electromagnetic susceptibility (EMS) difficulties are often identified in late stages of product development, causing unexpected additional costs of vehicles, electronic control units (ECUs), and integrated circuits (IC). To reduce such undesired costs, this letter presents an early stage placeEMS simulation of automotive IC which can be performed even before IC fabrication. Simulation before IC fabrication is important not only for IC vendors but also for first users of a new IC product because they often start the development of their own products (vehicles or ECUs) in the design stage of the new IC. An analog-to-digital converter (ADC) is chosen as the target circuit of this letter. It is a challenging target because the circuit is too complex to run numerous simulations for many diverse noise power and frequency points. The target is also sensitive even to very small (several-millivolt) noise. To run such challenging simulations with practical time and satisfactory accuracy, four key points are implemented: (1) consideration of the possible noise propagation paths, (2) simplified ADC model, (3) handling of nonlinearity, and (4) calculation of forward power. Simulation results show good consistency with measurement results obtained for two printed circuits boards (PCBs) by approximately 8 dB error in most frequency points. Consequently, the proposed simulation is helpful to reduce unexpected additional costs by predicting EMS risks and assessing the effects of the improvement method quantitatively in early product design stages.

A readout integrated circuit for sensitive infrared photodetection operating in intense backgrounds

Infrared photodetection generally presents some u.ndesirable features: low detector shunt resistance, large pixel dark current, high noise levels, and intense background signal. These impose challenges to design the readout integrated electronics to properly extract signal information from the detector, mainly due to the effect of low injection efficiency and the limited on-chip voltage supply. Signal sensitivity and saturation are, therefore, often compromised. This work presents the analysis of a readout integrated circuit, coined as the Bouncing Pixel, that prevents signal saturation and that is suitable for infrared electronics due to its high injection efficiency, high sensitivity of 51.65 mV/μA and high dynamic range of at least 105 dB. The simulation data presented in this work follows an application driven design flow for a CO2 gas detection system, considering real models for the infrared light source and the photodetector, optical modeling using the HITRAN database, and reliable readout integrated circuit simulation using device models for a standard TSMC CMOS 180 nm technology. Circuit noise analysis is included. Simulations show that the detection of a CO2 molar fraction as low as 3 ppm could be achieved, suggesting that the Bouncing Pixel is a good solution for high performance infrared readout integrated electronics, even with low chip supply voltages.

External electron injection, trapping, and emittance evolution in the blow-out regime

In this work, we study electron side-injection and trapping in the blow-out regime in deep plasma channels. We analyze the maximum angle of injection, for which at least 90% of the injected electrons are trapped. We discuss the dependence of this angle on the electrons' initial energy and their injection positions. In the scope of a semi-analytical blow-out model, we show that the injection position is a less critical factor for trapping if electrons are injected into deep plasma channels. Photonic integrated circuit simulations and analytical approximations support our results from the semi-analytical model. Furthermore, a discussion of the temporal evolution of the normalized radial emittance during the trapping process and further acceleration is presented.

Thermal modeling of 7 nm node bulk fin-shaped field-effect transistors for device structure-aware design

As semiconductor node technology becomes finer, the corresponding device dimensions should be reduced. To improve the side effects caused by the scaling-down strategy, fin-shaped field-effect transistors (FinFETs) have been introduced and are being actively researched. However, these thin silicon fins, especially confined within silicon dioxide (SiO2), have a relatively low thermal conductivity when compared with conventional planar bulk FETs. Thus, another issue, called the self-heating effect (SHE), has appeared with the emergence of FinFETs. In this paper, the self-heating effect on 7 nm node bulk FinFETs was investigated through calibrated technology computer-aided design (TCAD) simulation. A thermodynamic transport model is used to consider the self-heating effect on the device. The thermal resistance (RTH) was extracted from the TCAD result and modeled empirically to predict the RTH of sub-7 nm node technology. The empirical RTH model was also implanted in a Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG) to conduct an accurate Simulation Program with Integrated Circuit Emphasis (SPICE) model and simulation.

Novel thermal model of microchannel cooling system designed for fast simulation of liquid-cooled ICs

The research and design of liquid-cooled integrated circuits (IC) relies heavily on accurate simulation. Ideally, finite-element-method (FEM) based tools should be used for this purpose. However, in most cases a fully coupled thermo-fluidic simulation of complex ICs is very long, mostly due to the fact that the simulation of fluid dynamics is very time consuming. Therefore, in this paper we propose a novel model for thermal simulation of ICs cooled by integrated microchannels which significantly reduces the simulation time. The new approach is based on removing the fluid from the model and treating the solid-liquid boundary as a convective boundary, described by the convection equation. It is shown that the proposed model offers very good accuracy in steady-state, with errors below 3 °C in every chip point. In transient domain the results are equally good, with the maximum error around 3.3 °C (6% relative error). Moreover, the simulation times have been reduced by about two orders of magnitude with respect to fully coupled FEM simulation. However, the proposed model has also important limitations: currently ICs with only one layer of straight microchannels are supported and the model requires recalculation if some chip parameters are changed.

An analytical model for terahertz detection in cylindrical surrounding-gate MOSFETs

An analytical model for detection of terahertz radiation by plasma wave in cylindrical surrounding-gate (SRG) MOSFETs is presented. In comparison with traditional drain-current models, the rectification response of terahertz signal due to current self-mixing in conducting channel is considered by solving coupled plasma fluid equations using perturbation method. The resulted model is for the first time dipicting detector response in above threshold, near threshold and subthreshold regimes by a single expression valid for both resonant and nonresonant detection schemes. As no fitting parameters is adopted, the model is physical and predicative. Model validity has been extensively verified through numerically solving differential equations with a wide range of incident wave frequencies, channel doping concentrations, device working temperatures, SRG MOSFET geometry parameters as well as incident wave amplitudes. Model applicability to large input terahertz signal has also been discussed. The presented model is convenient for finding the optimum detector design from a multiparameter space. Its great universality will make it a candidate compact model for future terahertz integrated circuit simulation.

Temperature gradient‐aware thermal simulator for three‐dimensional integrated circuits

Nowadays, thermal simulators of integrated circuits (ICs) at architectural level tend to neglect thermal effects in temperature-dependent factors (such as leakage power and thermal conductivity) and a heat dissipation mechanism for thermal radiation at the early stages of IC design. Hence, the analysis results of thermal simulators may be not sufficient to reflect the physical–thermal interactive effects of ICs. This study presents a temperature gradient-aware thermal simulator for three-dimensional ICs (called 3D-TarGA) at the architectural level. The temperature gradient-aware thermal analysis of 3D-TarGA considers the thermal effects in leakage power, thermal conductivity, thermal radiation, and thermal convection to reflect the physical–thermal interactive effects of ICs at the early stages of IC design. Experimental results show that the maximum absolute error for the temperature of IC with ignoring the thermal effects using 3D-TarGA is 1.62°C, in contrast to the published thermal simulator, HotSpot. Moreover, the maximum absolute difference for the temperature of IC by considering the thermal effects is 2.7°C, as compared with that when ignoring the thermal effects for 3D-TarGA.

A 36 GHz HTS MMIC Josephson Mixer—Simulation and Measurement

Modeling, simulation, and measurement of a compact 36 GHz high-temperature superconducting (HTS) monolithic Josephson junction mixer are presented in this paper. A full HTS microwave monolithic integrated circuit (MMIC) simulation was carried out for the circuit combining HTS passive devices and the Josephson junction. Optimal impedance matching and bias conditions were investigated, and the circuit layout was designed accordingly. The HTS circuit has a compact dimension of 5 × 4 × 0.3 mm3, including filters, resonators, and impedance matching circuits. The HTS MMIC mixer was fabricated and packaged with an LNA to realize a receiver front end with a total dimension of 28 × 25 × 15 mm3. Measurement result showed an overall conversion gain around 35 dB, with local oscillator driving power around −45 dBm at operating temperature of 40 K.

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

This paper presents the design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial points. Those techniques are robust to any variations in the ECG signal with high sensitivity and precision. Two databases of the heart signal recordings from the MIT PhysioNet and the American Heart Association were used as a validation set to evaluate the performance of the processor. Based on application-specified integrated circuit (ASIC) simulation results, the overall classification accuracy was found to be 86% on the out-of-sample validation data with 3-s window size. The architecture of the proposed ESP was implemented using 65-nm CMOS process. It occupied 0.112- ${\rm mm}^{2}$ area and consumed 2.78- $\mu \text{W}$ power at an operating frequency of 10 kHz and from an operating voltage of 1 V. It is worth mentioning that the proposed ESP is the first ASIC implementation of an ECG-based processor that is used for the prediction of ventricular arrhythmia up to 3 h before the onset.

Simscape® based ultra-fast design exploration: graphene-nanoelectronic circuit case studies

SPICE has been the corner stone of integrated circuit simulation since the 1970s. The device-level options that are available for SPICE/analog simulators to simulate a circuit netlist are typically compact models and/or Verilog-A structural and behavioral models. Though these simulations are very accurate, for large and complex circuits/systems they are extremely slow and even computationally infeasible. Thus, as a paradigm shift of the conventional design simulation flow, this paper presents a complete Simscape®based design and simulation flow for ultra-fast design exploration of graphene based nanoelectronic systems. A behavioral model for a dual gate graphene field effect transistor (GFET) is modeled in Simscape®based on the drift-diffusion conduction mechanism. The kink region of the $$I-V$$I-V characteristic is modeled via a displacement current. For case study design circuits, an all graphene based low noise amplifier and an LC-tank voltage controlled oscillator are presented. The results show that the proposed design alternative to simulate analog circuits and systems is a viable option in addition to the existing SPICE, VHDL-AMS or Verilog-A based flows and can open the way to true device-level system design exploration and optimization. To the best of the authors' knowledge, this is the first ever paper to explore a Simscape®model of a GFET device and design a GFET based radio-frequency circuit using Simscape®.

A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations

To improve the efficiency of direct solution methods in SPICE-accurate integrated circuit (IC) simulations, preconditioned iterative solution techniques have been widely studied in the past decades. However, it is still an extremely challenging task to develop robust yet efficient general-purpose preconditioning methods that can deal with various types of large-scale IC problems. In this paper, based on recent graph sparsification research we propose circuit-oriented general-purpose support-circuit preconditioning (GPSCP) methods to dramatically improve the sparse matrix solution time and reduce the memory cost during SPICE-accurate IC simulations. By sparsifying the Laplacian matrix extracted from the original circuit network using graph sparsification techniques, general-purpose support circuits can be efficiently leveraged as preconditioners for solving large Jacobian matrices through Krylov-subspace iterations. Additionally, a performance model-guided graph sparsification framework is proposed to help automatically build nearly-optimal GPSCP solvers. Our experiment results for a variety of large-scale IC designs show that the proposed preconditioning techniques can achieve up to $18 {\times }$ runtime speedups and $7 {\times }$ memory reduction in DC and transient simulations when compared to state-of-the-art direct solution methods.

Photonic IC design software and process design kits

Abstract This review discusses photonic IC design software tools, examines existing design flows for photonics design and how these fit different design styles and describes the activities in collaboration and standardization within the silicon photonics group from Si2 and by members of the PDAFlow Foundation to improve design flows. Moreover, it will address the lowering of access barriers to the technology by providing qualified process design kits (PDKs) and improved integration of photonic integrated circuit simulations, physical simulations, mask layout, and verification.