SIMT Architecture Research Articles

APW: Asymmetric Padded Winograd to reduce thread divergence for computational efficiency on SIMT architecture

APW: Asymmetric Padded Winograd to reduce thread divergence for computational efficiency on SIMT architecture

GPU optimization of material point methods

The Material Point Method (MPM) has been shown to facilitate effective simulations of physically complex and topologically challenging materials, with a wealth of emerging applications in computational engineering and visual computing. Borne out of the extreme importance of regularity, MPM is given attractive parallelization opportunities on high-performance modern multiprocessors. Parallelization of MPM that fully leverages computing resources presents challenges that require exploring an extensive design-space for favorable data structures and algorithms. Unlike the conceptually simple CPU parallelization, where the coarse partition of tasks can be easily applied, it takes greater effort to reach the GPU hardware saturation due to its many-core SIMT architecture. In this paper we introduce methods for addressing the computational challenges of MPM and extending the capabilities of general simulation systems based on MPM, particularly concentrating on GPU optimization. In addition to our open-source high-performance framework, we also conduct performance analyses and benchmark experiments to compare against alternative design choices which may superficially appear to be reasonable, but can suffer from suboptimal performance in practice. Our explicit and fully implicit GPU MPM solvers are further equipped with a Moving Least Squares MPM heat solver and a novel sand constitutive model to enable fast simulations of a wide range of materials. We demonstrate that more than an order of magnitude performance improvement can be achieved with our GPU solvers. Practical high-resolution examples with up to ten million particles run in less than one minute per frame.

Using program branch probability for the thread parallelisation of branch divergence on the CUDA platform

Virtualisation environment can bring more flexibility for parallel optimisation. In view of this, we focus on the divergent branch problem within a SIMT architecture, where threads with branch divergence should be serially executed. Existing approaches are normally costly and not so satisfactory in vectorising these threads due to the constraints of private variables. However, on the other hand, these constraints can be released in a virtualised environment, because the private resources can be avoided putting in use directly by applications. For virtualised CUDA platforms, our approach can converge isomorphic threads into same redundant warps to eliminate divergence. We introduce the algorithms for the thread recombination models of binary branches, single branch and multiple branches respectively, and each number of redundant warps can be determined by a program branch probability. Without redesigning hardware needed, we obtained a load balance schema for parallelisation of divergent branch threads.

Using program branch probability for the thread parallelisation of branch divergence on the CUDA platform

Virtualisation environment can bring more flexibility for parallel optimisation. In view of this, we focus on the divergent branch problem within a SIMT architecture, where threads with branch divergence should be serially executed. Existing approaches are normally costly and not so satisfactory in vectorising these threads due to the constraints of private variables. However, on the other hand, these constraints can be released in a virtualised environment, because the private resources can be avoided putting in use directly by applications. For virtualised CUDA platforms, our approach can converge isomorphic threads into same redundant warps to eliminate divergence. We introduce the algorithms for the thread recombination models of binary branches, single branch and multiple branches respectively, and each number of redundant warps can be determined by a program branch probability. Without redesigning hardware needed, we obtained a load balance schema for parallelisation of divergent branch threads.

Efficient implementation of the many-body Reactive Bond Order (REBO) potential on GPU

The second generation Reactive Bond Order (REBO) empirical potential is commonly used to accurately model a wide range hydrocarbon materials. It is also extensible to other atom types and interactions. REBO potential assumes complex multi-body interaction model, that is difficult to represent efficiently in the SIMD or SIMT programming model. Hence, despite its importance, no efficient GPGPU implementation has been developed for this potential. Here we present a detailed description of a highly efficient GPGPU implementation of molecular dynamics algorithm using REBO potential. The presented algorithm takes advantage of rarely used properties of the SIMT architecture of a modern GPU to solve difficult synchronizations issues that arise in computations of multi-body potential. Techniques developed for this problem may be also used to achieve efficient solutions of different problems. The performance of proposed algorithm is assessed using a range of model systems. It is compared to highly optimized CPU implementation (both single core and OpenMP) available in LAMMPS package. These experiments show up to 6x improvement in forces computation time using single processor of the NVIDIA Tesla K80 compared to high end 16-core Intel Xeon processor.

SIMT구조 GP-GPU의 명령어 처리 성능 향상을 위한 Dispatch Unit과 Operand Selection Unit설계

본 논문은 그래픽 처리 뿐 만 아니라 범용 연산의 가속화를 지원하기 위한 SIMT 구조 GP-GPU의 Dispatch Unit과 Operand Selection Unit을 제안한다. Warp Scheduler로부터 발행된 명령어에서 사용되는 Operand의 모든 정보를 Decoding 하면 불필요한 Operand Load가 발생하여 레지스터 부하가 발생 한다. 이러한 문제점을 해결하기 위해 Pre-decoding방법을 사용하여 Operand의 정보만을 먼저 Decoding 하여 Operand Load를 줄이고, 레지스터의 부하를 줄일 수 있는 방법을 제안한다. 제안하는 Dispatch Unit에서 나온 Operand 정보들을 레지스터 뱅크 충돌을 방지하는 방법을 적용한 Operand Selection Unit에 전달해 전체적인 처리 성능을 향상 시켰다. Modelsim 10.0b를 이용하여 Warp Scheduler로부터 발행된 10,000개의 임의의 명령어를 처리하여 소요되는 총 Clock Cycle을 측정하였다. 본 논문에서 제안한 Pre-Decoding 기능을 탑재한 Dispatch Unit과 Operand Selection Unit을 적용하여 기존의 방법들 보다 각각 약 11%, 24%의 처리 효율이 증가한 것을 확인 할 수 있었다. This paper proposes a dispatch unit of GP-GPU with SIMT architecture to support the acceleration of general-purpose operation as well as graphics processing. If all the information of an operand used instructions issued from the warp scheduler is decoded, an unnecessary operand load occurs, resulting in register loads. To resolve this problem, this paper proposes a method that can reduce the operand load and the load on the resister by decoding only the information of the operand using a pre-decoding method. The operand information from the dispatch unit is passed to the operand selection unit with preventing register bank collisions. Thus the overall performance are improved. In the simulation test, the total clock cycles required by processing 10,000 arbitrary instructions issued from the wrap scheduler using ModelSim SE 10.0b are measured. It shows that the application of the dispatch unit equipped with the pre-decoding function proposed in this paper can make an improvement of about 12% in processing performance compared to the conventional method.

Heuristic Search Space Generation for Maximum Clique Problem Inspired in Biomolecular Filtering

Biomolecular filtering, as a computing paradigm, consists essentially of two steps: (1) the codification of candidate solutions in DNA and (2) the removal of non-valid solutions by means of biochemical procedures. The sticker model makes use of this notion, defining simple bitwise operations over large sets of DNA-coded binary strings. A sticker machine is conceived as a robotic station automatizing sticker operations and thus, can be seen as an SIMD computer with a densely populated pool of data. In this paper, the maximum clique problem is tackled by harnessing the massive threading of the CUDA SIMT architecture to replicate the parallel strand filtering. The proposed heuristic relies on the sequential-and-progressive generation of partial search spaces for subsequent parallel filtering in GPU. Computational results over DIMACS benchmark set show that our approach is competitive, compared to a preceding similar work and to state-of-the-art branch-and-bound algorithms. Moreover, our approach is scalable and produces more than one solution for some instances. As far as we know, the number of found cliques has not been previously used as a reference point for this problem.

Implementation of GP-GPU with SIMT Architecture in the Embedded Environment

Recent embedded processors become to be multi-cored, due to the increased power consumption by higher operating frequencies. Multi-core processors stimulate applications to be parallelized. Since general purpose CPU has small number of core, which is optimized for serial processing, it has a limitation of parallel processing. To overcome this limitation, GPU is used for the parallel processing. In this paper, we implement GP-GPU of SIMT architecture for parallel processing in the embedded environment. The performance of the implemented GP-GPU is compared with the existing multi-core CPU of the embedded environment. The comparison results show the performance of parallel processing with the implemented GP-GPU is improved significantly.

A Reconfigurable SIMT Processor for Mobile Ray Tracing With Contention Reduction in Shared Memory

In this paper, we present a reconfigurable SIMT multi-core processor with a shared memory for mobile ray tracing. The proposed processor addresses two issues of SIMT architecture: branch divergence of concurrently executed threads and contention in a shared memory. Performance degradation due to the branch divergence is reduced by dividing a wide SIMT datapath into several narrow SIMT cores that execute independent threads asynchronously. The contention in a shared memory caused by the multiple SIMT cores is alleviated by introducing a new time-division multiplexing (TDM) scheme using multi-phase clocks. The SIMT cores send their requests to a shared memory sequentially not concurrently by synchronizing the SIMT cores with multi-phase clocks to hide arbitration delays. The processor achieves the same datapath utilization as 4-wide SIMT which has been widely used by CPU-based ray tracers while its area remains 68% of the 4-wide SIMT. As a result, the performance normalized to area is improved by 26% compared to previous work with negligible overheads (2.6% for area and 1% for power consumption). The chip was fabricated in 90 nm CMOS technology, and it contains 2.3 M logic gates and 19.3 KB SRAM. It consumes 221 mW at 100 MHz with Vdd=1.2 V.

An 11 mm$^{2}$, 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12$\ \mu$m CMOS

With the rapid evolution of wireless standards and increasing demand for multi-standard products, the need for flexible RF and baseband solutions is growing. Flexibility is required to be able to adapt to unstable standards and requirements without costly hardware re-spins, and also to enable hardware reuse between products and between multiple wireless standards in the same device, ultimately saving both development cost and silicon area. In this paper a fully programmable baseband processor suitable for standards such as DVB-T/H and mobile WiMAX is presented. The processor is based on the SIMT architecture which utilizes a unique type of vector instructions to provide processing parallelism while minimizing the control complexity of the processor. The architecture has been demonstrated in a prototype chip which was proven in a complete DVB-T/H system demonstrator. The chip occupies 11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 0.12 mum CMOS process. It includes 1.5 Mbit of single port SRAM and 200 k logic gates. The measured power consumption for the highest DVB-T/H data rate (31.67 MBit/s) is 70 mW at 70 MHz. This outperforms both area and power figures of previously presented non-programmable DVB-T/H solutions.