Simplify Hardware Design Research Articles

Implementation of HD-SPWM Generation for Voltage Source Inverter Applications

The digital implementation of High-Definition Sinusoidal Pulse Width Modulation (HD-SPWM) achieves a higher accuracy and simplifies hardware design. To generate the digital PWM signal a single BRAM(Block Random Access Memory) is used. The memory allocation of the targeted FPGA device is reduced up to 43%. This reduces the number of slices (logic blocks) and LUTs, used for the implementation of HD-SPWM. The switching and sampling frequency for the generation of HD-SPWM are 20 kHz and 4 MHz respectively. The code is written in Verilog HDL and simulated in Modelsim and synthesized in Xilinx ISE. The Switching frequency achieved is 20 kHz respectively.

Architectural Design of a Fast Search Algorithm and Implementation to Intra-Mode Decision Block of Still Image Coding

As a requirement of many modern image compression standards faced today, a computational complexity is observed due to the best mode selection in the intra-prediction stage. This computational complexity is tried to be reduced by various techniques without affecting the performance criteria of the image. In this study, a fast search algorithm, which simplifies the mode selection process of the intra-prediction algorithm and provides calculation with less number of modes is proposed. The hardware architecture of this proposed algorithm is implemented for realization. There are two main sections of the intra-prediction algorithm in image compression, namely the image prediction process and the mode selection process. In this study, main objective is to reduce the process time of the mode selection and the simplification of the hardware design. Sum of absolute difference (SAD) is a frequently used criterion to simplify hardware design. The algorithm searches for the most suitable mode in a single step, where the decision is based on the SAD criterion preferred for the simplicity. The proposed algorithm and related hardware architecture is tested by using various experiments. The number of the modes calculated is reduced effectively, while the process is kept within the acceptable limits in terms of peak signal to noise ratio (PSNR) and compression rate (CR) performance criteria. Therefore, the number of clock cycles observed is considerably reduced. The designed architecture is synthesized for the field programmable gate arrays (FPGA) board and the obtained results are given. In addition, these results are compared with the HM reference software where the corresponding results are in accordance with the reference software.

Hardware implementation of spiking neural networks on FPGA

Inspired by real biological neural models, Spiking Neural Networks (SNNs) process information with discrete spikes and show great potential for building low-power neural network systems. This paper proposes a hardware implementation of SNN based on Field-Programmable Gate Arrays (FPGA). It features a hybrid updating algorithm, which combines the advantages of existing algorithms to simplify hardware design and improve performance. The proposed design supports up to 16 384 neurons and 16.8 million synapses but requires minimal hardware resources and archieves a very low power consumption of 0.477 W. A test platform is built based on the proposed design using a Xilinx FPGA evaluation board, upon which we deploy a classification task on the MNIST dataset. The evaluation results show an accuracy of 97.06% and a frame rate of 161 frames per second.

Power Converter With Digital Sensorless Adaptive Voltage Positioning Control Scheme

A digital sensorless adaptive voltage positioning (SLAVP) control method is presented in this paper in order to realize AVP control without the need for load or inductor current sensing and high-resolution high-speed analog-to-digital converter sampling. The SLAVP control law utilizes the readily available error signal of the conventional voltage-mode closed-loop compensated controller or, in other words, the duty cycle of a dc-dc buck converter in order to realize AVP control. The elimination of the need for high-speed and accurate sensing and sampling of currents using the proposed SLAVP control reduces the size and cost of the digital controller, reduces the power losses associated with current sensing and sampling, and simplifies hardware design. Moreover, the SLAVP control can easily be added to controllers with conventional voltage-mode closed-loop control with minimum size and cost increase, and therefore, SLAVP control can be used for a wide range of applications and not only for high-end applications like powering microprocessors. The theoretical SLAVP control law derivation and analysis and SLAVP controller architecture are presented in this paper and verified by experimental results obtained from a proof-of-concept experimental prototype.

Design of Insulation Resistance Test for Cables in Intelligent Munition

In the test system of intelligent munition, a test module of insulation resistance has been designed using the test resource of the system. The test module used virtual instrument technology,database technology and modularization method.It optimizes allocation of resources and simplifies hardware design. It has a good human-computer conversational enviroment and it is easy to operate and record for users. Introduced measuring methods of insulation resistance,designed hardware and measuring circuit,developed test software and realized the test data storage and management by using database technology.It realized automatic test.

Relax

As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whether exposing hardware fault information to software and allowing software to control fault recovery simplifies hardware design and helps technology scaling. The combination of emerging applications and emerging many-core architectures makes software recovery a viable alternative to hardware-based fault recovery. Emerging applications tend to have few I/O and memory side-effects , which limits the amount of information that needs checkpointing, and they allow discarding individual sub-computations with small qualitative impact. Software recovery can harness these properties in ways that hardware recovery cannot. We describe Relax, an architectural framework for software recovery of hardware faults. Relax includes three core components: (1) an ISA extension that allows software to mark regions of code for software recovery, (2) a hardware organization that simplifies reliability considerations and provides energy efficiency with hardware recovery support removed, and (3) software support for compilers and programmers to utilize the Relax ISA. Applying Relax to counter the effects of process variation, our results show a 20% energy efficiency improvement for PARSEC applications with only minimal source code changes and simpler hardware.

Implementation of a networked virtual nuclear magnetic resonance spectrometer

Virtual instrumentation offers several advantages over traditional instruments, such as the ability to simplify hardware design, the flexibility to easily change device function, and more recently,the ability to operate instrumentation from remote locations. In this article, a nuclear magnetic resonance (NMR) receiver is being developed using virtual instrumentation technology. In lieu of the analog technology used in traditional NMR instruments, a high-speed data acquisition board is used to directly digitize the radio-frequency (RF) NMR signal. This signal is then demodulated and processed from within LabVIEW®. Work is also being done so that the instrument can be operated over the Internet in a client–server mode. The resulting receiver was tested using both hardware- and software-simulated NMR signals. © 1998 National Instruments. Published by John Wiley & Sons, Inc. Lab Robotics and Automation 10: 115–118, 1998