Silicon Thin-film Transistors Research Articles

Investigation on operation robustness of p-type low-temperature polycrystalline silicon thin-film transistor-based micro light-emitting diode pixel circuit using pulse width modulation under component fluctuation

In this study, we have investigated the operation robustness of a p-type low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT)-based micro light-emitting diode (µLED) pixel circuit adopting pulse width modulation (PWM) under circuit component fluctuations. The wavelength shift of µLEDs, depending on the current density, was suppressed by implementing PWM. The PWM pixel circuit controlled the emission time with constant µLED current in the simulated and measured results. In addition, the wavelength shift was suppressed below 0.48% within the 10-bit grayscale range. Furthermore, the component tolerance of the pixel circuit was investigated by simulating the error rate of µLED emission time with varying threshold voltage, mobility, subthreshold swing, and capacitance. The pixel circuit exhibited a robust operation with a maximum error rate of 4.0% under a component fluctuation of ±10%. Consequently, the µLED pixel circuit adopting PWM suppressed the wavelength shift of µLEDs and demonstrated robust circuit operation under component fluctuation.

Improved Long-Term Stability of Low-Temperature Polysilicon Thin-Film Transistors by Using a Tandem Gate Insulator with an Atomic Layer of Deposited Silicon Dioxide

In this study, we report a substantial improvement in the long-term stability of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) with a tandem gate insulator composed of silicon dioxide (SiO2) deposited by using atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD). Negative-bias temperature instability (NBTI) tests showed that threshold-voltage (ΔVth) shifts were significantly smaller than when only a plasma-enhanced chemical vapor deposition (PECVD) structure was used. We believe that the unique stoichiometric characteristics and the reduction in the interfacial trap density (Dit) produced by the SiO2 gate insulator that had been fabricated using ALD enhanced the long-term stability of the LTPS TFTs. These results suggest a tandem structure gate insulator with high-quality ALD-based SiO2 thin film can provide an important improvement in the characteristics of the p-channel LTPS TFTs required for advanced active matrix organic light-emitting diodes (AMOLEDs) applications.

Reversely-Synchronized-Stress-Induced Degradation in Polycrystalline Silicon Thin-Film Transistors and Its Suppression by a Bridged-Grain Structure

In this letter, a reversely synchronized stress (RSS) is proposed to simulate the working condition of switching thin-film transistors (TFTs) in active-matrix displays. The reliability of polycrystalline silicon (poly-Si) TFTs under RSS is characterized and investigated. RSS brings huge device degradation. A dynamic hot carrier (HC) effect, dependent on transition edges of RSS, dominates the degradation. Combined with a transient simulation, the degradation mechanism under RSS in poly-Si TFTs is discussed and developed. To suppress RSS-induced HC degradation, a bridged-grain (BG) structure is employed in the active layer of poly-Si TFTs. Via BG lines’ reducing the lateral electric field in the channel at source/drain sides, the reliability of BG TFTs under RSS is significantly improved.

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage. The GIDL of fin-like TFTs (FinTFTs) examined in this study was dominated by longitudinal band-to-band tunneling (L-BTBT). Extending the wide drain can effectively suppress the longitudinal electric field near the drain and improve L-BTBT GIDL and breakdown. In addition, a wider drain can lead to a large cross section in the current path and improve the ON-state current. FinTFTs with wide drain exhibit a low GIDL, a high ON-state current, and high breakdown voltage, while maintaining favorable gate controllability.

Laser processing of thin-film multilayer structures: comparison between a 3D thermal model and experimental results.

In this research, a numerical model is introduced for simulation of laser processing of thin film multilayer structures, to predict the temperature and ablated area for a set of laser parameters including average power and repetition rate. Different thin-films on Si substrate were processed by nanosecond Nd:YAG laser pulses and the experimental and numerical results were compared to each other. The results show that applying a thin film on the surface can completely change the temperature field and vary the shape of the heat affected zone. The findings of this paper can have many potential applications including patterning the cell growth for biomedical applications and controlling the grain size in fabrication of polycrystalline silicon (poly-Si) thin-film transistors (TFTs).

19‐1: Invited Paper: Micro‐LED Microdisplays by Integration of III‐V LEDs with Silicon Thin Film Transistors

Emissive micro‐LED technologies have been a topic of recent interest as a means to build high‐luminance displays for direct‐view micro‐LED displays and micro‐LED microdisplays. The promise of an emissive technology coupled with the efficiency and luminance of III‐V LEDs has been studied for many years. With the prevalence of LEDs, the barrier for integration with transistor technologies to form arrays and display technologies has lowered. We present an overview of various micro‐LED technologies and our focus on micro‐LED microdisplays using our thin‐film integration method.

P‐23: Effect of Buffer Layers on Performance and Reliability of Polycrystalline Silicon TFTs Fabricated on Polyimide

Thickness of buffer layers affects performance of flexible polycrystalline silicon thin film transistors (TFT). A thicker buffer SiO2 film demonstrates better endurance to thermal expansion stress from the polyimide substrate. However, the thickness of buffer SiO2 film would causes the variation of optimal excimer laser annealing (ELA) crystallization condition. In addition, the simulation results shows that the non‐uniform stress in the gate insulator is more pronounced near the poly‐silicon/gate insulator edge and at the two sides of the poly‐silicon protrusion. It would affect the stability results and device performance. By optimization the process condition, the device would still have good device performance after operating under high temperature (60 □) and long period of time (500hrs).

Positive-Bias Temperature Instability Improvement of Poly-Si Thin-Film Transistor With HfO2 Gate Dielectric by Ammonia Plasma Treatment

In this paper, positive-bias temperature instability (PBTI) stress with different stress voltage at $T = 125~^{\circ }\text{C}$ is executed on the high-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with HfO2 gate dielectric and ammonia (NH3) plasma surface treatment. The NH3 plasma surface treatment on the poly-Si TFT with HfO2 gate dielectric can significantly decrease the threshold voltage ( $V_{\mathrm{ TH}}$ ) approximately −1.86 V, reduce the subthreshold slope (S.S.) approximately −88 mV/decade, enhance the transconductance ( $G_{m}$ ) approximately $2.4\times $ , and driving current ( $I_{\mathrm{ drv}})$ approximately 2.34. In addition, the device degradation after PBTI stress with stress voltage $V_{G} - V_{\mathrm{ TH}} = 7$ V for 1000 s at $T = 125~^{\circ }\text{C}$ can also be improved after the NH3 plasma surface treatment, such as the suppressing of $V_{\mathrm{ TH}}$ shift from 2.063 to 0.617 V, S.S. degradation quantity from 0.284 V/decade to 0.172 V/decade, and $I_{\mathrm{ drv}}$ reduction from −77% to −44%. The improvement of the PBTI of poly-Si TFTs with NH3 plasma surface treatment is attributed to the suppression of oxide charge trapping effect and the degradation of interface state density ( $N_{\mathrm{ it}}$ ) and grain boundary trap state density ( $N_{\mathrm{ GB}}$ ).

Dynamic-Gate-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

In this paper, degradation behaviors of bridged-grain (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are systematically characterized and investigated. Device degradation exhibits a two-stage behavior, which is related to pulse falling time ( $t_{f}$ ). A faster $t_{f}$ brings a larger ON-current ( $I_{\mathrm{\scriptscriptstyle ON}}$ ) increase in the first stage and a larger $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage. Electron trapping/injection into gate oxide and dynamic hot carrier effect are found to be responsible to $I_{\mathrm{\scriptscriptstyle ON}}$ increase in the first stage and $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage, respectively. Compared with normal poly-Si TFTs, BG poly-Si TFTs show much more reliable performance under the same dynamic gate stress. The larger $I_{\mathrm{\scriptscriptstyle ON}}$ increase in the first stage in BG poly-Si TFTs is attributed to the enhanced vertical electric field in the channel near the gate oxide, while the much smaller $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage is attributed to lateral electric field reduction caused by the sharing of the field across multiple reversely biased junctions inside the active channel. Incorporated with transient simulations, the degradation mechanisms for both the first stage and the second stage are elucidated. In addition, the impact of the first-stage degradation on the second-stage degradation is also clarified.

Electrical Properties of Bottom Gate Poly-Si TFTs by NiSi2 Seed-Induced Lateral Crystallization and Its Applications

ABSTRACT In this paper, the electrical properties of bottom-gate (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) by NiSi2 seed-induced lateral crystallization (SILC) and its applications are presented. Sequential lateral solidification (SLS), which is one of crystallization methods, is known to have poor electrical properties of TFTs with BG structures due to problems induced by laser. Therefore, the laser method cannot be used to well-developed production line of amorphous-Si (a-Si) TFT, resulting in large initial investment cost to change fabrication procedures. On the other hand, the BG poly-Si TFT by SILC (SILC-BGPS TFT) has basically compatible process flows with that of the a-Si TFT. The SILC-BGPS TFT exhibited threshold voltage of -3.9 V, steep subthreshold slope of 130 mV/dec, a high field-effect mobility of 129 cm2/Vs , and I on /I off ratio of ∼106.

A High-Current Kink Effect Free Z-Gate Poly–Si Thin-Film Transistor

In this letter, a high-current kink effect free Z-gate polycrystalline silicon (poly-Si) thin-film transistor (ZG-TFT) is proposed and demonstrated. The ZG-TFT, which is formed by a raised source/drain (RSD) region and a split channel (SC) structure, reveals better device performance. Our experimental results show that the ON-current of ZG-TFT is about two times higher than that of a conventional single top gate TFT, and the leakage current is greatly reduced simultaneously. In addition, the high drain electric field is considerably reduced by the RSD structure, and the SC design can further effectively suppress the kink effect. Therefore, a better ON/OFF current ratio and a higher drain breakdown voltage can be achieved.

A Comparison of Photo-Induced Hysteresis Between Hydrogenated Amorphous Silicon and Amorphous IGZO Thin-Film Transistors.

We investigate photo-induced instability in thin-film transistors (TFTs) consisting of amorphous indium-gallium-zinc-oxide (a-IGZO) as active semiconducting layers by comparing with hydrogenated amorphous silicon (a-Si:H). An a-IGZO TFT exhibits a large hysteresis window in the illuminated measuring condition but no hysteresis window in the dark condition. On the contrary, a large hysteresis window measured in the dark condition in a-Si:H was not observed in the illuminated condition. Even though such materials possess the structure of amorphous phase, optical responses or photo instability in TFTs looks different from each other. Photo-induced hysteresis results from initially trapped charges at the interface between semiconductor and dielectric films or in the gate dielectric which possess absorption energy to interact with deep trap-states and affect the movement of Fermi energy level. In order to support our claim, we also perform CV characteristics in photo-induced hysteresis and demonstrate thermal-activated hysteresis. We believe that this work can provide important information to understand different material systems for optical engineering which includes charge transport and band transition.

Improving transistors with nanomaterials

Device Technology High-performance silicon transistors and thin-film transistors used in display technologies are fundamentally limited to miniaturization. Incorporating nanomaterials—such as carbon nanotubes, graphene, and related two-dimensional materials like molybdenum disulfide—into these devices as gate materials may circumvent some of these limitations. Franklin reviews the opportunities and challenges for incorporating nanomaterials into transistors to improve performance. Because high-performance transistors are distinct from thin-film transistors, incorporating them into flexible or transparent platforms raises new challenges. Science , this issue [10.1126/science.aab2750][1] [1]: /lookup/doi/10.1126/science.aab2750

Direct-Conversion X-Ray Detector with 50-µm High-Gain Pixel Amplifiers for Low-X-Ray-Dose Digital Mammography

This study proposes an active pixel sensor (APS) design for readout signal amplification to replace the traditional passive pixel sensor (PPS) design. The APS design adds only one extra thin-film transistor (TFT) amplifier, giving it the high signal sensitivity of the APS architecture and the high spatial resolution of the PPS architecture. The mobility of the amorphous silicon (a-Si) TFT is 0.56 cm2/Vs, the signal amplification of the APS circuit is more than 10×, the on/off current ratio is more than 107, and the leakage current is on the order of 1 fA. A 200-µm-thick layer of amorphous selenium (a-Se) as the X-ray photoconductor was deposited on the APS array with 160 × 160 pixels of various sizes, down to 50 µm. The 40-kVp X-ray spectra obtained with tube currents of 40 and 50 mA, respectively, were used for measuring the gray-level contrast induced by the X-rays. The experimental results show that the gray-level contrasts for the 50-µm pixels were 5.57 ± 0.89 and 13.19 ± 1.94 and those for the 70-µm pixels were 15.94 ± 2.98 and 24.19 ± 2.76 under 40-kVp X-ray exposure at 40 and 50 mA, respectively.

Improvement of the Electrical Characteristics of a-Si:H TFTs Using the Phosphorus Doping in the Active Layer

This paper suggests a method of phosphorus doping in the active layer to improve the electrical characteristics of hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT). Phosphorus doping in the active layer of a-Si:H was performed by the deposition of a-Si:H through the addition of phosphine gas by plasma enhanced chemical vapor deposition (PECVD). We confirmed that the electrical characteristics of phosphorus doped a-Si:H TFT were improved compared to those of conventional a-Si:H TFT to the extent that the field effect mobility and off current were 0.44 cm2/V•s and 1.53 × 10−12 cm2 when phosphorus was doped by 1 sccm. We investigated the sheet resistance (Rs), root-mean-square roughness (RMS) and density of state (DOS) to demonstrate the improved electrical characteristics. From the results, we confirmed that phosphorus doping in the active layer supplies the electron to use dopant in the channel as well as leads to an improvement of the DOS and higher quality in a-Si:H.

Low-temperature poly-silicon thin-film transistor developed without ion doping

Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) were developed without ion doping for lower cost. Aluminum (Al), a group 3 element, was used for the source and drain regions instead of ion doping. The effect of Al doping was verified through the Arrhenius plot to check the shift of the Fermi level. Al doping was applied for the metal-induced lateral crystallized polycrystalline silicon (Si) to achieve a p-channel LTPS TFT without ion doping. The TFT developed via Al doping exhibited 35.5 cm2/V s field effect mobility, a−3.7 V threshold voltage (Vth), a 4.0×105 on–off ratio, and a 0.7 V/dec subthreshold slope.

35.4: Programmable Pulse Width LTPS TFT Shift Register for High Resolution and High Frame Rate Active Matrix Flat Panel Displays

AbstractThis paper proposes a programmable pulse width LTPS TFT shift register where an output pulse width is programmed only by adjusting a start pulse width without any additional clock signals and reconfiguration. Since an overlap interval of the output pulses is easily controlled in the shift register which operates with precharging scheme, the proposed shift register can be applied to high resolution and high frame rate display without the problem of insufficient line time. The performance of this circuit is verified by SMART SPICE at low‐temperature poly silicon (LTPS) thin film transistor (TFT) process. The pulse width is changed by the step size of two line time with only two input clock signals which leads to small area for circuit implementation and simulated power consumption is similar to that of the conventional shift register.

Impact of the Inhomogenous Structure of Polysilicon TFT's Active Layer on the Electrostatic Potential Distribution

Recently polycrystalline silicon (pc-Si) thin film transistors (TFT’s) have emerged as the devices of choice for many applications. The TFTs made of a thin un-doped polycrystalline silicon film deposited on a glass substrate by the Low Pressure Chemical Vapor Deposition technique LPCVD have limits in the technological process to the temperature < 600°C. The benefit of pc-Si is to make devices with large grain size. Unfortunately, according to the conditions during deposition, the pc-Si layers can consist of a random superposition of grains of different sizes, where grains boundaries parallels and perpendiculars appear. In this paper, the transfer characteristics IDS-VGS are simulated by solving a set of two-dimensional (2D) drift-diffusion equations together with the usual density of states (DOS: exponential band tails and Gaussian distribution of dangling bonds) localized at the grains boundaries. The impact of thickness of the active layer on the distribution of the electrostatic potential and the effect of density of intergranular traps states on the TFT’s transfer characteristics IDS-VGS have been also investigated.

Amorphous Silicon Thin Film Transistor Biosensing System

ABSTRACTElectronic systems are a very good platform for sensing biological signals for fast point-of-care diagnostics or threat detection. One of the solutions is the lab-on-a-chip integrated circuit (IC), which is low cost and high reliability, offering the possibility for label-free detection. In recent years, similar integrated biosensors based on the conventional complementary metal oxide semiconductor (CMOS) technology have been reported. However, post-fabrication processes are essential for all classes of CMOS biochips, requiring biocompatible electrode deposition and circuit encapsulation.In this work, we present an amorphous silicon (a-Si) thin film transistor (TFT) array based sensing approach, which greatly simplifies the fabrication procedures and even decreases the cost of the biosensor. The device contains several identical sensor pixels with amplifiers to boost the sensitivity. Ring oscillator and logic circuits are also integrated to achieve different measurement methodologies, including electro-analytical methods such as amperometric and cyclic voltammetric modes. The system also supports different operational modes. For example, depending on the required detection arrangement, a sample droplet could be placed on the sensing pads or the device could be immersed into the sample solution for real time in-situ measurement. The entire system is designed and fabricated using a low temperature TFT process that is compatible to plastic substrates. No additional processing is required prior to biological measurement. A Cr/Au double layer is used for the biological-electronic interface. The success of the TFT-based system used in this work will open new avenues for flexible label-free or low-cost disposable biosensors.

Logic Gates and Ring Oscillators Based on Ambipolar Nanocrystalline-Silicon TFTs

Nanocrystalline silicon (nc-Si) thin film transistors (TFTs) are well suited for circuit applications that require moderate device performance and low-temperature CMOS-compatible processing below 250°C. Basic logic gate circuits fabricated using ambipolar nc-Si TFTs alone are presented and shown to operate with correct outputs at frequencies of up to 100 kHz. Ring oscillators consisting of nc-Si TFT-based inverters are also shown to operate at above 20 kHz with a supply voltage of 5 V, corresponding to a propagation delay of <10 μs/stage. These are the fastest circuits formed out of nanocrystalline silicon TFTs to date. The effect of bias stress degradation of TFTs on oscillation frequency is also explored, and relatively stable operation is shown with supply voltages >5 V for several hours.