Silicon Planar Transistors Research Articles

Design of Negative Resistance Oscillator with Rocord Low Phase Noise

The aim of this paper is to use a new design of a negative resistance microwave oscillator in order to fabricate oscillator with very good performance in terms of output power, efficiency, stability and phase noise. In this study the new concept of oscillator using distributed resonator and micro-strip circuit elements improve performances of our structure. A micro-strip microwave oscillator with low phase noise based on an NPN silicon planar epitaxial transistor has been designed, fabricated, and characterized. In this design, each step has been conducted by using Advanced Design System (ADS) and following a theoretical study which enable to optimize the different performances of the whole circuit. The oscillator produce a sinusoidal signal with spectrum power of 12.25 dBm at 2.45 GHz into 50 Ω load when polarized at Vcc=15V with DC to RF efficiency of 16. The obtained phase noise of -120 dBc/Hz at 100 Hz offset is the result of the use of high Q factor resonator and the depth study of the parameters of the oscillator. Simulation and measurement results are in good agreement.

Improvement in electrical properties of high-κ film on Ge substrate by an improved stress relieved pre-oxide method

High-κ/Ge gate stack has recently attracted a great deal of attention as a potential candidate to replace planar silicon transistors for sub-22 generation. However, the desorption and volatilization of GeO hamper the development of Ge-based devices. To cope with this challenge, various techniques have been proposed to improve the high-κ/Ge interface. However, these techniques have not been developed perfectly yet to control the interface. Therefore, in this paper, we propose an improved stress relieved pre-oxide (SRPO) method to improve the thermodynamic stability of the high-κ/Ge interface. The x-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM) results indicate that the GeO volatilization of the high-κ/Ge gate stack is efficiently suppressed after 500 °C annealing, and the electrical characteristics are greatly improved.

Desorption kinetics of GeO from GeO2/Ge structure

High-κ dielectrics on Ge have recently attracted much attention as a potential candidate to replace planar silicon transistors for sub-32-nm generations. However, the instability of the high-κ/Ge interface, especially the desorption of germanium monoxide (GeO), hampers the development of Ge-based devices. Therefore, the typical GeO2/Ge structure was chosen to investigate GeO desorption. In this contribution, we describe the desorption kinetics of GeO, including Ge/GeO2 interface reaction, the diffusion process during GeO desorption, the desorption activation energy of GeO, the different mechanisms of GeO desorption, and the active oxidation of Ge. Through annealing GeO2/Ge in an ultrahigh vacuum (UHV), direct evidence for the consumption of Ge substrate has been shown by atomic force microscopy (AFM) measurements of the consumption depth. By using thermal desorption spectroscopy (TDS) measurements and studying oxygen-18 isotope tracing, we have clarified that the GeO desorption is not caused by the GeO direct-diffusion process. Isothermal TDS measurements and morphology investigation have revealed a transition from a uniform desorption mechanism to a nonuniform one as GeO2 thickness was reduced. On the basis of the experimental results in this study, a GeO desorption model has been developed. For GeO desorption, about 2 eV of activation energy has been obtained from kinetic calculation on the basis of TDS analysis. Different from the UHV annealing, the active oxidation of Ge has been observed by AFM measurements under low oxygen partial pressures.

Atomic layer deposition of hafnium oxide on germanium substrates

Germanium combined with high-κ dielectrics has recently been put forth by the semiconductor industry as potential replacement for planar silicon transistors, which are unlikely to accommodate the severe scaling requirements for sub-45-nm generations. Therefore, we have studied the atomic layer deposition (ALD) of HfO2 high-κ dielectric layers on HF-cleaned Ge substrates. In this contribution, we describe the HfO2 growth characteristics, HfO2 bulk properties, and Ge interface. Substrate-enhanced HfO2 growth occurs: the growth per cycle is larger in the first reaction cycles than the steady growth per cycle of 0.04nm. The enhanced growth goes together with island growth, indicating that more than a monolayer coverage of HfO2 is required for a closed film. A closed HfO2 layer is achieved after depositing 4–5HfO2 monolayers, corresponding to about 25 ALD reaction cycles. Cross-sectional transmission electron microscopy images show that HfO2 layers thinner than 3nm are amorphous as deposited, while local epitaxial crystallization has occurred in thicker HfO2 films. Other HfO2 bulk properties are similar for Ge and Si substrates. According to this physical characterization study, HfO2 can be used in Ge-based devices as a gate oxide with physical thickness scaled down to 1.6nm.

Solid Logic Technology: Versatile, high-performance microelectronics

A new microelectronics packaging technique, called Solid Logic Technology (SLT), utilizes silicon planar glass-encapsulated transistors and diodes, and graphic arts techniques for producing high-quality, passive components having tight tolerances. The result is a process permitting the low-cost realization of a variety of versatile, high-performance circuit modules. The salient features of SLT are described: the unique form of the semiconductor devices, the module fabrication process, and some performance results. In addition, insight is provided to the range of components that my be fabricated with this technology, i.e., inductors, capacitors and high-power transistors. Examples are shown of specific high-speed, high-density and complex circuit packages.

Correlation between 1/f noise and h/sub FE/ long-term instability in silicon bipolar devices

Accelerated life tests with high-temperature storage and electric aging for n/sup +/-p-n silicon planar transistors were carried out. Current gain h/sub FE/ increases monotonously with time during the tests, and the h/sub FE/ drift is correlated with initial measured 1/f noise in the transistors, i.e. the drift amount significantly increases with the increase of noise level. The correlation coefficient of relative drift Delta h/sub FE//h/sub FE/ and 1/f noise spectral density S/sub iB/(f) is far larger than that of Delta h/sub FE//h/sub FE/ and initial DC parameters of the transistors. A quantitative theory model for the h/sub FE/ drift has been developed and explains the h/sub FE/ drift behavior in the tests, which suggests that the h/sub FE/ drift and 1/f noise can be attributed to the same physical origin, and both are caused by the modulation of the oxide traps near the Si-SiO/sub 2/ interface to Si surface recombination. 1/f noise measurement, therefore, may be used as a fast and nondestructive means to predict the long-term instability in bipolar transistors. >

Magnetic induction transducers based on silicon planar transistors

The paper presents the results of studies and development of silicon planar transducers of constant and variable magnetic field induction into an electric signal. The transistors have magneto-sensitive area within the volumes of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> -10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . The dependences of transport coefficient on electric field intensity in the base area as well as current and voltage magneto-sensitivity are given. They are 250 μA.T <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</inf> =5mA) and 50 V.T <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> for the transducers of tangential component of induction and 30 μA.T <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</inf> =5mA) and 30 V.T <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> for the transducers of normal component induction.

Noise measurement analysis of NPN transistors after gamma irradiation—An investigation for reliability

Electrical noise characteristic of semiconductor devices like transistors, zener diodes and linear integrated circuits was presented in my earlier paper[3]. The present paper deals with the behaviour of noise levels after gamma radiation in the case of NPN silicon planar transistors. Noise level of these transistors increases significantly after the dose level of 10 5 R.

Generation of nanosecond high-voltage pulses with high repetition rate

The letter presents a circuit for the generation of 50 V pulses with 1.2 ns rise time, 2.5 ns duration and a variable pulse repetition frequency up to 3 MHz based on the effect of avalanche multiplication. The use of standard epitaxial silicon planar transistors instead of selected avalanche types permits safe operation with low sensitivity to temperature variations.

Emitter diffusion-induced stress effect on common-emitter current gain of silicon planar transistors

Emitter diffusion-induced stress effect on common-emitter current gain of silicon planar transistors

Effects of emitter diffusion-induced stresses on the common-emitter current gain of silicon planar transistors

physica status solidi (a)Volume 51, Issue 1 p. K83-K88 Short Note Effects of emitter diffusion-induced stresses on the common-emitter current gain of silicon planar transistors N. D. Stojadinović, N. D. Stojadinović Faculty of Electronic Engineering, University of Niš Search for more papers by this authorS. D. Ristić, S. D. Ristić Faculty of Electronic Engineering, University of Niš Search for more papers by this author N. D. Stojadinović, N. D. Stojadinović Faculty of Electronic Engineering, University of Niš Search for more papers by this authorS. D. Ristić, S. D. Ristić Faculty of Electronic Engineering, University of Niš Search for more papers by this author First published: 16 January 1979 https://doi.org/10.1002/pssa.2210510155Citations: 5 Beogradska 14, 18000 Niš, Yugoslavia. AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Citing Literature Volume51, Issue116 January 1979Pages K83-K88 RelatedInformation

Some effects of localized stress on silicon planar transistors

It is shown that the common-emitter current gain is significantly increased under high pressure (in the range of elasticity) when a uniform pressure is applied to a part of the emitter. Under the same conditions base and collector currents are increased, as well as the saturation voltage, while the breakdown voltage collector-emitter is decreased. All theoretical results are checked experimentally. [Russian Text Ignored]

On the fall time of silicon planar transistors with constant base current drive

In the active region transient response of a transistor in common emitter configuration with constant base current drive, there is some discrepancy in theoretically predicted and experimentally observed fall time. It has been explained by taking into account an additional turn-off base current drive which is usually ignored due to the emitter-base voltage of the transistor in the fall time expression using charge-control model of the transistor. The calculated values of the fall time of various silicon planar transistors are verified experimentally.

Current gain degradation induced by emitter-base avalanche breakdown in silicon planar transistors : A. J. Melia. Microelectron. Reliab.15, 619 (1976)

In this study, we investigated various highly porous extracellular matrix (ECM)-based cryogels for cartilage tissue engineering. For the fabrication of ECM-based cryogels, either methacrylated chondroitin sulfate (MeCS) or methacrylated hyaluronic acid (MeHA) were cross-linked along with poly (ethylene glycol) diacrylates (PEGDA) via free radical polymerization under freezing conditions. This procedure induces ice crystallization (used as a porogen) prior polymer crosslinking in which, after complete cryopolymerization, a thawing process transforms the ice crystals into a unique interconnected macroporous structure within ECM-cryogels. The developed ECM-cryogels exhibited an average macroporosity of 75% and supported the infiltration of chondrocyteds. When rabbit chondrocytes were cultured on ECM-cryogels, MeCS-based cryogels stimulated aggrecan gene expression and GAG accumulation, whereas MeHA-based cryogels stimulated type II collagen gene expression and collagen accumulation. These results demonstrate that design of ECM-based cryogels can play an important role in promoting specific ECM proteins secretion for cartilage tissue engineering.

Current gain degradation induced by emitter-base avalanche breakdown in silicon planar transistors

The operation of silicon planar transistors under emitter-base avalanche breakdown conditions can cause drastic reductions in current gain. Having investigated the dependence of the degradation rates on avalanche current for two types of n- p- n transistor, the mechanism, carrier injection into the protective oxide is explained, and experimental data from tests on 300 transistors is compared with published theory.

Active element in submerged repeaters: first quarter century

The review links the development of British submarine telephony during the last 25 years with the development and production of the active elements, thermionic valves and silicon planar transistors, in the submerged repeater amplifiers. These devices have played a major role in determining the performance, capacity and reliability of all submarine transmission systems. While concentrating on the work of the British Post Office Research Department the complementary role played by industry, and by Standard Telephones and Cables in particular, is recognised. British effort has been encouraged and stimulated throughout by the other major submarine development organisation, Bell Telephone Laboratories in the USA. The development in France of active devices for submarine systems has also been noteworthy. The work on oxide-cathode thermionic valves between 1950 and 1965 is mainly the history of a research and development effort aimed at improving the electrical reliability of the devices. Only in the latter part of the period was any major attempt made to improve valve performance and, consequently, the capacity of submarine systems. The use of systems incorporating valves extends from shallow-water cables around the UK to transatlantic and trans-Pacific cables which have completed a transmission link more than half-way round the world. The target of a 20-year system life, free from failures arising from the decay or collapse in the performance of the valves, has already been achieved for one of the early systems. One of the major links (CANTAT-1, between the UK and Canada) has now passed the 14th year of service satisfactorily. The era of silicon planar transistors, replacing the thermionic valves in submarine systems, started in 1961 and is still continuing. The twin targets of improving performance and reliability were equally stressed during the whole period from 1961 to date. The success in improving device performance is demonstrated by the capacity of the early transistorised systems, 640 (3kHz) circuits, almost double that achieved in the last valve system. Transistor performance has improved still further to provide 1840 circuits in the last transatlantic cable (CANTAT-2, laid in 1974) and later device developments will more than double this figure. The importance of this achievement rests, however, on the maintenance of ultrahigh reliability as an essential feature of performance improvement. An advanced technique for reliability assessment has enabled predictions of less than one active-element failure in a system life of 20 years to be made. It has only been possible to reach this level of reliability by careful design of the transistor and of the processes by which it is made, supplemented by a rigorous system of quality control imposed on materials, piece parts and assembly techniques. Experience of the first eight years of operational use on the sea bed is supporting the reliability predictions. For the future, it is believed that the foundations necessary to support the British effort in this important area of international communications have been well laid. Nevertheless, technical innovation is needed more than ever before to maintain a competitive position in the face of increasing overseas interest in the art of submarine telephony.

Current gain recovery in silicon nitride passivated planar transistors by hydrogen implantation

During deposition of silicon nitride, the low-current h <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</inf> of silicon planar transistors decreases. When the nitride layer completely seals the oxide from the ambient, the initial value of h <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</inf> cannot be restored by annealing at 500°C in forming gas. To eliminate this difficulty, hydrogen ions have been implanted at an energy of 70 keV and at doses varying from 1.10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> to 1.10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> through the nitride into the oxide. Optimum h <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</inf> recovery has been obtained with implantation at a dose of 3.10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> followed by a radiation damage annealing at 400-500°C in dry nitrogen.

Subnanosecond-pulse generator with variable pulsewidth using avalanche transistors

The letter describes a pulse generator with epitaxial silicon planar transistors working in the avalanche-breakdown mode. The risetime is 150 ps and the fall time 200 ps. The pulse-width can be varied continuously between 0.3 and 120 ns, without changing the maximum amplitude of about 15 V. Simple rules for the exact design of the circuitry are given.

226. Choice of regimes of preparation of n-p-n silicon planar transistors with application of the ion implantation method: I D Goloto et al, Izv VUZ Radioelektron, 16 (4), 1973, 92–94 ( in Russian)

226. Choice of regimes of preparation of n-p-n silicon planar transistors with application of the ion implantation method: I D Goloto et al, Izv VUZ Radioelektron, 16 (4), 1973, 92–94 ( in Russian)

Reliability assurance of individual semiconductor components

Where small numbers of highly reliable semiconductor devices are required, conventional methods of procurement are found to have deficiencies. An approach to procurement is proposed which is cost effective, accommodates new device types, and assures reliability in the individual device. Although principally applied to silicon planar transistors, the approach can be extended to other semiconductor types. A critical evaluation is made of the manufacturer and his technology. The devices obtained from each diffused wafer are grouped into separate lots. Selected tests are performed on these lots in order to discover possible failure mechanisms. Tests may involve simple electrical measurements or detailed techniques such as scanning electron microscopy and X-ray microprobe analysis. The Canadian/U.S.A. Communications Technology Satellite (CTS) program has adopted this procurement procedure.