Silicon Photonic Links Research Articles

High-coherence parallelization in integrated photonics

Coherent optics has profoundly impacted diverse applications ranging from communications, LiDAR to quantum computations. However, developing coherent systems in integrated photonics comes at great expense in hardware integration and energy efficiency. Here we demonstrate a high-coherence parallelization strategy for advanced integrated coherent systems at minimal cost. By using a self-injection locked microcomb to injection lock distributed feedback lasers, we achieve a record high on-chip gain of 60 dB with no degradation in coherence. This strategy enables highly coherent channels with linewidths down to 10 Hz and power over 20 dBm. The overall electrical-to-optical efficiency reaches 19%, comparable to that of advanced semiconductor lasers. This method supports a silicon photonic communication link with an unprecedented data rate beyond 60 Tbit/s and reduces phase-related DSP consumption by 99.99999% compared to traditional III-V laser pump schemes. This work paves the way for realizing scalable, high-performance coherent integrated photonic systems, potentially benefiting numerous applications.

OML-PCM: optical multi-level phase change memory architecture for embedded computing systems

Unlike Dynamic Random Access Memory (DRAM), Phase Change Memory (PCM) offers higher density, longer data retention, and improved scalability because of its non-volatility and low leakage power. However, Electrically-Addressable PCM (EPCM) has a higher dynamic power and long latency than DRAM. To address these issues, scientists have developed Optically-Addressable PCM (OPCM), which uses 5-level cells instead of 2-level cells in EPCM. A silicon photonic link allows optical signals to reach OPCM cells at a high speed. Hence, OPCM can achieve a higher density while maintaining better performance at multi-level cells and consuming less power per access. However, OPCM is not suitable for general use since the photonic links do not provide an electrical interface to the processor. The aim of this paper is to present a hybrid OPCM architecture based on the use of novel multi-bank clusters with distinctive properties. Electrical-Optical-Electrical conversion (EOE) allows OPCM cells to be randomly accessed by using DRAM-like circuitry. The proposed hybrid design with multi-core processing and OPCM achieves a 2.13x speedup over previous approaches while consuming less Central Processing Unit (CPU) power. It is important to note that the proposed design offers 97 units fewer power-consistent bits than EPCM. In addition, the proposed architecture provides comparable performance and power to DDR4, as well as improved bandwidth density, space efficiency, and versatility. The Gem5 simulator was used to evaluate the design. Based on the outcomes of the analysis, the proposed architecture offers 2.08x and 2.14x better evaluations and density performance than EPCM. Furthermore, the execution time has been reduced by 2.13x, the analysis time by 1.23x, and the composition time by 4.60%.

Massively scalable Kerr comb-driven silicon photonic link

The growth of computing needs for artificial intelligence and machine learning is critically challenging data communications in today’s data-centre systems. Data movement, dominated by energy costs and limited ‘chip-escape’ bandwidth densities, is perhaps the singular factor determining the scalability of future systems. Using light to send information between compute nodes in such systems can dramatically increase the available bandwidth while simultaneously decreasing energy consumption. Through wavelength-division multiplexing with chip-based microresonator Kerr frequency combs, independent information channels can be encoded onto many distinct colours of light in the same optical fibre for massively parallel data transmission with low energy. Although previous high-bandwidth demonstrations have relied on benchtop equipment for filtering and modulating Kerr comb wavelength channels, data-centre interconnects require a compact on-chip form factor for these operations. Here we demonstrate a massively scalable chip-based silicon photonic data link using a Kerr comb source enabled by a new link architecture and experimentally show aggregate single-fibre data transmission of 512 Gb s−1 across 32 independent wavelength channels. The demonstrated architecture is fundamentally scalable to hundreds of wavelength channels, enabling massively parallel terabit-scale optical interconnects for future green hyperscale data centres.

Scaling comb-driven resonator-based DWDM silicon photonic links to multi-Tb/s in the multi-FSR regime

The use of chip-based micro-resonator Kerr frequency combs in conjunction with dense wavelength-division multiplexing (DWDM) enables massively parallel intensity-modulated direct-detection data transmission with low energy consumption. Resonator-based modulators and filters used in such systems can limit the number of usable wavelength channels due to practical constraints on the maximum achievable free spectral range (FSR). In this work, we introduce the design of multi-Tb/s comb-driven resonator-based silicon photonic links by leveraging the multi-FSR regime. We demonstrate the viability of the link architecture with yield estimates that are supported by extensive wafer-scale measurements of 704 micro-resonators fabricated in a commercial complementary metal–oxide–semiconductor foundry. We show that a 2.80 Tb/s link is realizable with a ≥6σ yield (∼99.999%), and that aggregate bandwidths of 3.76 Tb/s and 4.72 Tb/s are possible if yield targets are relaxed (3σ and 1σ, respectively). All designs represent a 1.94−3.28× boost to aggregate link bandwidth while maintaining BER≤10−10 performance, with a theoretical bandwidth of 10.51 Tb/s being possible for sufficiently robust resonators. We use high-speed BER measurements to inform co-optimization of data rate and aggressor spacing (λag), limiting any additional loss-based power penalties to off-resonance insertion loss (IL) and routing loss. This work demonstrates that, through the multi-FSR regime, there is a clear path toward Kerr comb-driven ultra-broadband, high bandwidth silicon photonic links that can support next-generation data centers and high-performance computers.

Architecting Optically Controlled Phase Change Memory

Phase Change Memory (PCM) is an attractive candidate for main memory, as it offers non-volatility and zero leakage power while providing higher cell densities, longer data retention time, and higher capacity scaling compared to DRAM. In PCM, data is stored in the crystalline or amorphous state of the phase change material. The typical electrically controlled PCM (EPCM), however, suffers from longer write latency and higher write energy compared to DRAM and limited multi-level cell (MLC) capacities. These challenges limit the performance of data-intensive applications running on computing systems with EPCMs. Recently, researchers demonstrated optically controlled PCM (OPCM) cells with support for 5 bits / cell in contrast to 2 bits / cell in EPCM. These OPCM cells can be accessed directly with optical signals that are multiplexed in high-bandwidth-density silicon-photonic links. The higher MLC capacity in OPCM and the direct cell access using optical signals enable an increased read/write throughput and lower energy per access than EPCM. However, due to the direct cell access using optical signals, OPCM systems cannot be designed using conventional memory architecture. We need a complete redesign of the memory architecture that is tailored to the properties of OPCM technology. This article presents the design of a unified network and main memory system called COSMOS that combines OPCM and silicon-photonic links to achieve high memory throughput. COSMOS is composed of a hierarchical multi-banked OPCM array with novel read and write access protocols. COSMOS uses an Electrical-Optical-Electrical (E-O-E) control unit to map standard DRAM read/write commands (sent in electrical domain) from the memory controller on to optical signals that access the OPCM cells. Our evaluation of a 2.5D-integrated system containing a processor and COSMOS demonstrates 2.14 × average speedup across graph and HPC workloads compared to an EPCM system. COSMOS consumes 3.8× lower read energy-per-bit and 5.97× lower write energy-per-bit compared to EPCM. COSMOS is the first non-volatile memory that provides comparable performance and energy consumption as DDR5 in addition to increased bit density, higher area efficiency, and improved scalability.

ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip

The approximate computing paradigm advocates for relaxing accuracy goals in applications to improve energy-efficiency and performance. Recently, this paradigm has been explored to improve the energy-efficiency of silicon photonic networks-on-chip (PNoCs). Silicon photonic interconnects suffer from high power dissipation because of laser sources, which generate carrier wavelengths, and tuning power required for regulating photonic devices under different uncertainties. In this article, we propose a framework called AppRoXimation framework for On-chip photonic Networks (ARXON) to reduce such power dissipation overhead by enabling intelligent and aggressive approximation during communication over silicon photonic links in PNoCs. Our framework reduces laser and tuning-power overhead while intelligently approximating communication, such that application output quality is not distorted beyond an acceptable limit. Simulation results show that our framework can achieve up to 56.4% lower laser power consumption and up to 23.8% better energy-efficiency than the best-known prior work on approximate communication with silicon photonic interconnects and for the same application output quality.

Ultra-Broadband Interleaver for Extreme Wavelength Scaling in Silicon Photonic Links

We demonstrate an ultra-broadband silicon photonic interleaver capable of interleaving and de-interleaving frequency comb lines over a 125 nm bandwidth in the extended C- and L-bands. We use a ring-assisted asymmetric Mach Zehnder interferometer to achieve a flat-top passband response while maintaining a compact device footprint. The device has a 400 GHz free spectral range to divide an optical frequency comb with 200 GHz channel spacing into two output groups, each with a channel spacing of 400 GHz, yielding a potential capacity of 78 total wavelength-division multiplexed channels between 1525 nm and 1650 nm. This device represents an important step towards realizing highly parallel integrated optical links with broadband frequency comb sources within the silicon photonics platform.

Design Considerations for Energy Efficient DWDM PAM4 Transceivers Employing Avalanche Photodiodes

AbstractAn effective approach to increase per‐fiber bandwidth is to combine per‐wavelength four‐level pulse amplitude modulation (PAM4) with dense wavelength division multiplexing (DWDM). Silicon photonic transceivers based on microring resonator modulators and drop filters can allow for an efficient realization of this. Utilizing avalanche photodiodes (APDs) in the receiver front‐ends of these transceivers can significantly improve sensitivity, allowing for reduced source laser power and overall improved power efficiency. This paper analyzes the optical‐modulation amplitude (OMA) sensitivity of these APD‐based PAM4 receivers in a silicon photonic DWDM link. A comprehensive link budget is considered that takes into account various system losses and relevant noise sources. Modeling with a developed APD that has a maximum 230 GHz gain‐bandwidth product predicts sensitivity improvements at 32 to 64 Gb s−1 PAM4 ranging from 9.8 to 12 dB relative to a conventional p‐i‐n photodiode. Scaling the APD gain‐bandwidth to 310 GHz allows support of 112 Gb s−1 with −13.2 dBm OMA sensitivity at a BER of with an APD gain of 10. Utilizing the presented architecture, link budget analysis predicts a 9.5x reduction in laser power with APDs and that 38 mW source laser optical power can support a four‐channel DWDM link operating at an aggregate 448 Gb s−1 data rate.

Modeling and Optimization of Hybrid FinFET-Silicon Photonic Interconnects

Optical links have emerged as the best solution for short-reach communications (down to tens of meters), both in terms of speed and power consumption. In order to reduce energy-per-bit consumptions and enhance data rates, new technologies (for modulators, packaging, etc.) are being developed.Before implementing them into commercial products, it is essential to evaluate the impact of these new technologies on the overall performance of a link. In this work, a benchmarking tool is developed to optimize the design of electrical transceivers and to minimize the energy-per-bit consumption of a silicon photonic optical link integrated with CMOS FinFET transceivers. This tool is used to compare three stacking technologies (C4 bumps, micro-bumps and bump-less stacking) and evaluate their impacts on an optical link's data rate and power consumption. For this study, a silicon ring modulator is used to modulate the light from a laser, and all components of the link are designed such that a bit-error-rate of $ 10^{-12}$ is achieved. This work shows that replacing conventional C4 bumps by a bump-less stacking interface extends the bandwidth of an optical link from 45 Gbps to 65 Gbps, and reduces the energy-per-bit consumption from 2 pJ/bit to 0.6 pJ/bit at 45 Gbps.

A Laser-Forwarded Coherent Transceiver in 45-nm SOI CMOS Using Monolithic Microring Resonators

For the silicon photonic links to meet the target bit error rate (BER), the laser source must output enough optical power to overcome the optical channel loss and limited receiver sensitivity. Combined with poor wall-plug efficiency, this optical power requirement makes the electrical power consumed by the laser source a significant portion of the link energy cost. This article proposes a laser-forwarded coherent link that greatly reduces the required laser optical power by averaging optical path loss between the main and forwarded paths and by improving the receiver sensitivity using a homodyne coherent detector. The link performance analysis reveals that the laser forwarded link improves the laser power budget by ≈6-8 dB compared with a conventional intensity-modulation/direct detection link using typical photonic link components. To demonstrate the laser forwarded link, a microring resonator phase modulator, a balanced detector, and a 3-dB coupler are integrated with CMOS circuits in a GFUS 45-nm SOI process. The transmit driver and the receiver consume 40 and 450 fJ/bit, respectively. Aided by ≈8-dB boost from laser forwarding and the coherent detection gain, the receiver achieves -15.6-dBm optical modulation amplitude sensitivity. The link operates at 10 Gb/s with BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> and electrical energy efficiency of 2.3 pJ/bit.

A Silicon Photonic Data Link with a Monolithic Erbium-Doped Laser

To meet the increasing demand for data communication bandwidth and overcome the limits of electrical interconnects, silicon photonic technology has been extensively studied, with various photonics devices and optical links being demonstrated. All of the optical data links previously demonstrated have used either heterogeneously integrated lasers or external laser sources. This work presents the first silicon photonic data link using a monolithic rare-earth-ion-doped laser, a silicon microdisk modulator, and a germanium photodetector integrated on a single chip. The fabrication is CMOS compatible, demonstrating data transmission as a proof-of-concept at kHz speed level, and potential data rate of more than 1 Gbps. This work provides a solution for the monolithic integration of laser sources on the silicon photonic platform, which is fully compatible with the CMOS fabrication line, and has potential applications such as free-space communication and integrated LIDAR.

Performance Requirements for Terabit-Class Silicon Photonic Links Based on Cascaded Microring Resonators

The electrical interconnects in high performance computing (HPC) systems are reaching their bandwidth capacities in supporting data-intensive applications. Currently, communication between compute nodes through these interconnects is the main bottleneck for overall HPC system performance. Optical interconnects based on the emerging silicon photonics (SiP) platform are considered to be a promising replacement to boost the speed of the data transfer with reduced cost and energy consumption compared to electrical interconnects. In this paper, we present a comprehensive analysis of a comb source microring-based SiP link architecture with p-i-n photodetectors. In particular, we direct our focus on improved grating coupler and bus waveguide designs to reduce the link power penalties. Additionally, we map the required performance from the comb laser to provide an aggregated data rate of 1 Tbps under the constraints of free spectral range (FSR) and nonlinearities of the microring resonators (MRRs). We show that a select few comb configurations satisfy these requirements, and energy consumption as low as 3 pJ/bit is achievable.

Energy Efficiency Analysis of Comb Source Carrier-Injection Ring-Based Silicon Photonic Link

Current electronic interconnections in high performance computing (HPC) systems are reaching their limit in supporting high data traffic demands. Dense wavelength-division multiplexed (DWDM) links have gained interest as they can potentially alleviate these interconnect bandwidth demands while also lowering the cost and energy consumption compared to traditional electronic links. In this article we present an analysis of a ring-based DWDM silicon photonic (SiP) link architecture with a comb laser source and p-i-n photodetectors. Specifically, we consider microring resonators (MRRs) with narrow bus waveguides and carrier-injection ring modulators. We propose a new method to select the optimal comb source setting to minimize the laser power consumption at a particular data rate. Additionally, we leverage power penalty models supported by measurements to estimate the effective received optical power at the receiver input of each of the DWDM channels which yields a bit error rate (BER) of $\text{10}^{-{\text{12}}}$ or lower. We show that the analyzed comb source has the lowest power consumption per channel for 24 consecutive lines. For these comb settings, the maximum channel data rate of non-return to zero on-off keying (NRZ-OOK) signals is 22 Gbps, and the minimum energy consumption is 3.28 $\frac{\text{pJ}}{\text{bit}}$ .

Electronic–Photonic Co-Optimization of High-Speed Silicon Photonic Transmitters

System-level driven electronic–photonic codesign is the key to improving the bandwidth density and energy efficiency for high-speed silicon photonic links. In many data-communication scenarios, optical link power is dominated by its transmitter side including the laser source. In this paper, we propose a comprehensive co-optimization framework for high-speed silicon photonic transmitters utilizing compact models and a detailed optical simulation framework. Given technology and link constraints, microring and Mach–Zehnder transmitter designs are optimized and compared based on a unified optical phase shifter model. NRZ and PAM4 modulation schemes are analyzed and compared for microring-based transmitters at 50 Gb/s. Multistage and traveling wave Mach–Zehnder transmitters are optimized and discussed as well. The results show that, for a 50 Gb/s NRZ optical link, an optimized microring transmitter could save more than 60% of the total laser and driver power compared to an optimized Mach–Zehnder transmitter under equivalent photonic technology constraints. For a given datarate and receiver sensitivity, design tradeoffs of silicon photonic processes, devices, and architecture choices are discussed in depth. In addition, this paper introduces a new Simulink toolbox for transient optical simulation. Combined with the proposed optimization engine, it provides an electrooptical co-optimization approach toward truly energy-efficient high-speed silicon photonic links.

Comprehensive Design Space Exploration of Silicon Photonic Interconnects

The paper presents a comprehensive physical layer design and modeling platform for silicon photonic interconnects. The platform is based on explicit closed-form expressions for optical power penalties, derived for both signal-dependent and signal-independent noise contexts. Our models agree well with reported experimental measurements. We show how the modeling approach is used for the design space exploration of silicon photonic links and can be leveraged to optimize the wavelength-division multiplexed (WDM) capacity, evaluate the scalability, and study the sensitivity of the system to key device parameters. We apply the methodology to the design of microring-based silicon photonic links, including an evaluation of the impairments associated with cascaded ring modulators, as well as the spectral distortion and crosstalk effects of demultiplexer ring arrays for nonreturn-to-zero (NRZ) ON–OFF keying (OOK) modulated WDM signals. We show that the total capacity of a chip-to-chip microring-based WDM silicon photonic link designed with recently reported interconnect device parameters can approach 2 Tb/s realized with NRZ-OOK data modulation and 45 wavelengths each modulated at 45 Gb/s.

Managing Laser Power in Silicon-Photonic NoC Through Cache and NoC Reconfiguration

In manycore systems, the silicon-photonic link technology is projected to replace electrical link technology for global communication in network-on-chip (NoC) as it can provide as much as an order of magnitude higher bandwidth density and lower data-dependent power. However, a large amount of fixed power is dissipated in the laser sources required to drive these silicon-photonic links, which negates any bandwidth density advantages. This large laser power dissipation depends on the number of on-chip silicon-photonic links, the bandwidth of each link, and the photonic losses along each link. In this paper, we propose to reduce the laser power dissipation at runtime by dynamically activating/deactivating L2 cache banks and switching ON/OFF the corresponding silicon-photonic links in the NoC. This method effectively throttles the total on-chip NoC bandwidth at runtime according to the memory access features of the applications running on the manycore system. Full-system simulation utilizing Princeton application repository for shared-memory computers and Stanford parallel applications for shared-memory-2 parallel benchmarks reveal that our proposed technique achieves on an average 23.8% (peak value 74.3%) savings in laser power, and 9.2% (peak value 26.9%) lower energy-delay product for the whole system at the cost of 0.65% loss (peak value 2.6%) in instructions per cycle on average when compared to the cases where all L2 cache banks are always active.

An all-solid-state, WDM silicon photonic digital link for chip-to-chip communications.

We describe a multiwavelength hybrid-integrated solid-state link on a 3 µm silicon-on-insulator (SOI) nanophotonic platform. The link spans three chips and employs germanium-silicon electroabsorption waveguide modulators, silicon transport waveguides, echelle gratings for multiplexing and demultiplexing, and pure germanium waveguide photo-detectors. The 8λ WDM Tx and Rx components are interconnected via a routing "bridge" chip using edge-coupled optical proximity communication. The packaged, retimed digital WDM link is demonstrated at 10 Gb/s and 10(-12) BER, with three wavelength channels consuming an on-chip power below 1.5 pJ/bit, excluding the external laser power.

A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS

Silicon-photonics is an emerging technology that can overcome the tradeoffs faced by traditional electrical I/O. Due to ballooning development costs for advanced CMOS nodes, however, widespread adoption necessitates seamless photonics integration into mainstream processes, with as few process changes as possible. In this work, we demonstrate a silicon-photonic link with optical devices and electronics integrated on the same chip in a 0.18 µm bulk CMOS memory periphery process. To enable waveguides and optics in process-native polysilicon, we introduce deep-trench isolation, placed underneath to prevent optical mode leakage into the bulk silicon substrate, and implant-amorphization to reduce polysilicon loss. A resonant defect-trap photodetector using polysilicon eliminates need for germanium integration and completes the fully polysilicon-based photonics platform. Transceiver circuits take advantage of photonic device integration, achieving 350 fJ/b transmit and 71 µA pp BER = 10 -12 receiver sensitivity at 5 Gb/s. We show high fabrication uniformity and high-Q resonators, enabling dense wavelength-division multiplexing with 9-wavelength 45 Gb/s transmit/receive data-rates per waveguide/fiber. To combat perturbations to variation- and thermally-sensitive resonant devices, we demonstrate an on-chip thermal tuning feedback loop that locks the resonance to the laser wavelength. A 5 m optical chip-to-chip link achieves 5 Gb/s while consuming 3 pJ/b and 12 pJ/bit of circuit and optical energy, respectively.

Energy-Efficient Photonics in Future High-Connectivity Computing Systems

Energy-efficiency has become a critical parameter in the design of high-performance computing systems. Typically, compute elements consume the most energy in current systems, with memories and interconnect networks close behind. This paper proposes an energy-efficient, high-connectivity, petascale computing system for the year 2020 timeframe by addressing the energy requirements of these three components. We start with projections based on purely evolutionary computer system design trends, then include the impact of breakthroughs in processor design, memory packaging and optical interconnect technologies. Based on these projections, we motivate the development for a 1-pJ/b optical intrasystem interconnect technology that significantly increases system interconnect bandwidth and relieves the distance-based energy dependence of electrical alternatives. We show that improvements in compute, memory, and IO, when simultaneously applied, become a vision for many-chip photonically-interconnected modules that could lead to an order of magnitude improvement in energy efficiency in the 2020 timeframe. The vision hinges on a high-density, energy-efficient optical link that can connect electronic compute and memory elements across short chip-to-chip distances while also capable of kilometer or longer spans across data centers. We discuss the power budget to enable such a link and review experimental progress toward creating an ultra-dense, hybrid-integrated low-power silicon photonic link that will enable this vision.

Efficient WDM Laser Sources Towards Terabyte/s Silicon Photonic Interconnects

Efficient multi-wavelength sources are essential to realize sub-pJ/bit modulated silicon photonic links for multi-TB/s interconnect applications. From a complete link perspective, we discuss the efficiency requirement for silicon WDM on-chip sources. A waveguide-coupled wall-plug efficiency (WPE) better than 10% is important to complement ultra-low power silicon photonic components for practical implementations. We propose a non-invasive hybrid, flip-chip integration approach using surface-normal coupling of an un-cooled III/V gain medium with a tunable wavelength selective silicon reflector. We show that a tunable, external-cavity WDM laser using such a hybrid integration approach can achieve high waveguide-coupled WPE when optimized. A proof-of-concept demonstration achieved a C-band tunable laser with an output power of more than 6 mW in the silicon waveguide, a tuning range of 15 nm, and a WPE of over 4.5%.