Silicon Gate CMOS Process Research Articles

High speed pattern matching for a fast Huffman decoder

The fast Huffman decoding algorithm has been used in JPEG, MPEG and image data compression standards, etc. And code compression is a key element in high speed digital data transport. A major compression is performed by converting the fixed-length codes to variable-length codes through an entropy coding scheme. Huffman coding combined with run-length coding is shown to be a very efficient coding scheme. To speed up the process of search for a symbol in a Huffman tree and to reduce the memory size we have proposed a tree clustering and a pattern matching algorithm to avoid high sparsity of the tree. The method is shown to be very efficient in memory size and fast searching for the symbol. For an experimental video data with Huffman codes extended up to 16 bits in length, i.e. it is used for the standard JPEG, the result of experiments show that the proposed algorithm has a very high speed and performance. The design of the decoder is carried out using silicon-gate CMOS process. >

Defect characterization of a silicon gate CMOS process : Jacques Laneuville, Jean Marcoux, Jon Orchard-Webb and Alain Comeau. Semiconductor Int. 250 (May 1985)

Defect characterization of a silicon gate CMOS process : Jacques Laneuville, Jean Marcoux, Jon Orchard-Webb and Alain Comeau. Semiconductor Int. 250 (May 1985)

A 1.5 V CMOS 4-bit microcomputer needs only 100 /spl mu/W

Describes a new 4-bit microcomputer fabricated using a low-power silicon gate CMOS process and working from a supply voltage down to 1.2 V. The /spl mu/C can directly drive up to seven 3:1 multiplexed LCD digits, scan up 48 keys, and perform 4-bit handshaking data transfer with external devices. 16-bit, single-word instructions and eight stack levels permit efficient use of the 640-word ROM. Operating from a 4.19 MHz crystal, the device has an instruction cycle time of 15 /spl mu/s. An operating power of 100 /spl mu/W at 1.5 W makes the chip ideal for performing control and timing functions in battery operated applications.

An integrated single-chip PCM voice codec with filters

A new single-chip monolithic compressed/expanded (companded) pulse-code modulation (PCM) coder/decoder (codec) is described. The associated switched-capacitor filters and reference voltage are also implemented on the chip, using a silicon-gate CMOS process. The DAC and ADC used incorporate a binary-weighted capacitor array and a string of equal-valued resistors. The circuit operators from a/spl plusmn/5 V supply and it consumes 65 mW in normal operation and 5 mW in the power-down condition. The implementation of the critical circuits in CMOS technology is discussed in detail.

1.5 V 1 K-CMOS-RAM with only 8 pins

A 256-bit/spl times/4-bit static RAM working on a supply voltage down to 1.2 V is described. A serial interface for the address and the data with a 4-bit bus reduces the pincount of the RAM to only 8. Special design techniques to reach the design goal-very low power at a reasonable circuit speed-are discussed in detail. The device is fabricated in a low power silicon gate CMOS process. An operating power of 500 /spl mu/W/MHz and a standby power of less than 1 /spl mu/W at 1.5 V supply voltage was achieved. With this serial interface a cycle time of 1 /spl mu/s at 1.5 V was measured.

Silicon Gate CMOS on Bulk Silicon for Ionizing Radiation Environments

A silicon gate CMOS process on bulk silicon has been developed which can normally be applied to any production circuit and raise its intrinsic hardness to ionizing radiation environments to at least 5 × 104 Rads-Si. This is an order of magnitude above the failure level of most commercial CMOS integrated circuits. Dry oxidation of the silicon along with heavy P-well surface concentration is used to obtain this result, with the only penalty being a small increase in gate propagation delay. Both circuit upset and latchup levels are also improved with this radiation-hardened silicon gate CMOS process.