Signed-digit Number Arithmetic Research Articles

Residue-weighted number conversion using signed-digit number for moduli set {22n − 1, 22n+1 − 1, 2 n }

By introducing a signed-digit (SD) number arithmetic into a residue number system, arithmetic operations can be performed efficiently. In this paper, a new residue-to-binary conversion algorithm for three-moduli set {22n ? 1, 22n+1 ? 1, 2 n } using the residue SD number addition is proposed. Based on the proposed algorithm, the converter can be designed with only four high-speed SD number adders. The comparison of the proposed converter using SD number arithmetic with the converter using binary arithmetic yields more efficient both in terms of area and time.

RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2n-1, 2n + 1, 22n + 1, 2n} USING SIGNED-DIGIT NUMBER

Signed-digit number systems support carry-free, constant time addition. By introducing the signed-digit number arithmetic into a residue number system (RNS), arithmetic operations can be performed efficiently. In this paper, a new algorithm for residue-to-binary conversion for four moduli set {2n-1, 2n + 1, 22n + 1, 2n} that only requires modulo 24n - 1 SD number addition is proposed. This moduli set has 5n-bit dynamic range. Based on the proposed algorithm, the converters are designed with a two-level binary tree structure formed by the modulo 24n - 1 SD number residue adders. Moreover, we simplify the residue adders in converters to obtain more area and time efficiency. The comparison of the converters proposed with the converter using binary arithmetic using 0.18 μm CMOS gate array technology yields reductions in delays of 44%, 60% and 75% for n = 4, n = 8 and n = 16, respectively.

New Booth Modulo m Multipliers with Signed-Digit Number Arithmetic

New modulo m multipliers with a radix-two signed-digit (SD) number arithmetic is presented by using a modified Booth recoding method. To implement a modulo m multiplication, we usually generate modulo m partial products, then perform modulo m sum of them. In this paper, a new Booth recoding method is proposed to convert a radix-two SD number into a recoded SD (RSD) number in parallel. In the RSD number representation, there are no (1, 1)and (-1, -1) at any two-digit position. Thus, by using the RSD converted, the modulo m partial products can be cut from n into n/2 for an n × n modulo m multiplication. Parallel and serial modulo m multipliers have been designed by using the SD number arithmetic and the proposed Booth recoding. Compared to the former work, the area for VLSI implementation of the parallel modulo m multiplier is reduced to 80% from the original design, and the speed performance of the serial multiplier is improved up to twice by using the Booth recoding. The implementation method of the proposed Booth modulo m multipliers has been verified by a gate level simulation.