Signal Switching Activity Research Articles

Impact of place and route strategy on FPGA electromagnetic emission

As technology scales down, dense integration and high operating frequencies associated with increased number of I/O buffers are factors contributing to electromagnetic emission (EME) increase of FPGA devices. Noting that the EME depends not only on the dynamic power dissipated by the device, but also on the coupling degree between the layout of the routed tracks and the signal switching activity along with these tracks, it is of high interest and challenging to investigate FPGA EME performance. With this purpose, this paper presents an analysis about the impact of the placement and routing (P&R) process of logic inside the FPGA on the chip EME level. With this goal in mind, a softcore processor was placed and routed based on three different strategies in the configurable logic block (CLB) array of a commercial FPGA and executed an application code running over an operating system (OS). One of these P&R strategies is performed automatically by a commercial CAD tool, whose results are compared against the other two manually P&R processes of the FPGA. Two experiments have been performed. The obtained results indicate that the EME level can be affected up to 21.8% by the way the processor is placed and routed inside the FPGA. In this scenario, we suggest to improve the efficiency of the commercial CAD tool to execute the P&R process by having in mind the FPGA EME.

Clock Gated Single-Edge-Triggered Flip-Flop Design with Improved Power for Low Data Activity Applications

In this paper, the proposed flip-flop reduces power consumption by reducing the clock switching power that was wasted otherwise. Unlike many other gated flip-flops, the proposed gated flip-flop has state retention property to save power and to switch circuit between idle and active modes smoothly. The feedback path is also improved in the proposed flip-flop to decrease power dissipation. The proposed clock-gating scheme only requires 4 transistors, thus occupies the small silicon area. Further, the proposed clock gating network can be shared among a group of flip-flops to reduce the power and area overhead of the gating network. The simulation results show that for all supply voltages, the proposed flip-flop has the least power dissipation among all the designs for low switching activities. The proposed flip-flop has up to 7.82 times power improvement than the existing flip-flops. However, for 100% data activity, the proposed FF consumes up to 2.71 times power than the existing flip-flops. The proposed clock gated flip-flop structure is best suited for applications where input signal switching activity is low and speed is not a crucial factor.

Applying real-time interface and calculus for dynamic power management in hard real-time systems

Power dissipation has been an important design issue for a wide range of computer systems in the past decades. Dynamic power consumption due to signal switching activities and static power consumption due to leakage current are the two major sources of power consumption in a CMOS circuit. As CMOS technology advances towards deep sub-micron domain, static power dissipation is comparable to or even more than dynamic power dissipation. This article explores how to apply dynamic power management to reduce static power for hard real-time systems. We propose online algorithms that adaptively control the power mode of a system, procrastinating the processing of arrived events as late as possible. To cope with multiple event streams with different characteristics, we provide solutions for preemptive earliest-deadline-first and fixed-priority scheduling policies. By adopting a worst-case interval-based abstraction, our approach can not only tackle arbitrary event arrivals, e.g., with burstiness, but also guarantee hard real-time requirements with respect to both timing and backlog constraints. We also present extensive simulation results to demonstrate the effectiveness of our approaches.

Dynamic power reduction of FPGA-based reconfigurable computers using precomputation

This paper examines the effectiveness of employing precomputation techniques to reduce power consumption of field configurable computing systems. Multiplier is modified with precomputation techniques and are implemented using commercial off-the-shelf FPGAs. Precomputation techniques reduce dynamic power consumption of a module by eliminating unnecessary signal switching activities in inactive portions of the modules. Experiments have shown that up to 52% of logic and signal power consumption can be reduced in multiplier module. Furthermore, when compared to ASIC implementations, FPGA implementations of precomputation modules have the advantage of lower area overhead as most of them can be implemented using originally unoccupied related FPGA resources. Finally, it was found that the effectiveness of precomputation depends heavily on the input data statistics. It is expected that compilers for future reconfigurable computers may take full advantage of such power saving techniques by optimizing the architecture according to data input statistics.

Timing- and crosstalk-driven area routing

We present a timing- and crosstalk-driven router for the chip assembly task that is applied between global and detailed routing. Our new approach aims to process the crosstalk and timing constraints by ordering nets and tuning wire spacing in a quantitative way. The new approach fits between global routing and detailed routing along the physical design flow. It is the first to address the timing- and crosstalk-driven area routing problem using crosspoint assignment prior to the detailed routing stage, in contrast to the most previous approaches applied in the post-detailed routing stage. Our new approach enjoys a larger optimization solution space than the previous approaches whose solution space is highly limited by routed geometric constraints. Based on the global routing information, our graph-based optimizer preroutes wires on the global routing grids incrementally. The graph-based optimizer has two stages, net order assignment and space relaxation. A quick capacitance extraction and Elmore delay calculator considering signal switching activities are implemented to find the timing of critical nets and to provide the timing slack database of critical nets. As the graph-based algorithm proceeds, the path delay of critical nets and the timing slack database are updated. During the optimization process, it only optimizes the timing critical paths with negative slack values. The experimental results show a 5%-16% delay reduction for MCNC macrocell benchmark circuits for a 0.25 /spl mu/m process for wire geometric ratio (height/width)=1.0, against a 25% delay reduction if there is infinite space around each metal wire on the same layer.

Architectural and compiler techniques for energy reduction in high-performance microprocessors

In this paper, we focus on low-power design techniques for high-performance processors at the architectural and compiler levels. We focus mainly on developing methods for reducing the energy dissipated in the on-chip caches. Energy dissipated in caches represents a substantial portion in the energy budget of today's processors. Extrapolating current trends, this portion is likely to increase in the near future, since the devices devoted to the caches occupy an increasingly larger percentage of the total area of the chip. We propose a method that uses an additional minicache located between the I-Cache and the central processing unit (CPU) core and buffers instructions that are nested within loops and are continuously otherwise fetched from the I-Cache. This mechanism is combined with code modifications, through the compiler, that greatly simplify the required hardware, eliminate unnecessary instruction fetching, and consequently reduce signal switching activity and the dissipated energy. We show that the additional cache, dubbed L-Cache, is much smaller and simpler than the I-Cache when the compiler assumes the role of allocating instructions to it. Through simulation, we show that for the SPECfp95 benchmarks, the I-Cache remains disabled most of the time, and the cheaper extra cache is used instead. We also propose different techniques that are better adapted to nonnumeric nonloop-intensive code.