Signal Component Separator Research Articles

Inphasing Signal Component Separation for an X-Band Outphasing Power Amplifier

This work investigates signal component separator design for an RF-input outphasing power amplifier (RFIO PA). In the RFIO architecture, the phase- and amplitude-modulated input signals to the outphasing power stage are realized using a nonlinear “inphasing” network, resulting in an outphasing system that operates on a single RF input. Previous RFIO work has demonstrated the feasibility of this approach, but the combined nonlinear effects of the inphasing and outphasing networks have resulted in overall poor linearity. In this work, we use a simplified transistor model to predict the inphasing network design requirements, and then compare three nonlinear components to synthesize the required transfer function. An $X$ -band monolithic microwave-integrated circuit (MMIC) in 150-nm GaN is used as the output stage, and its operation is characterized for hybrid inphasing networks based on three different technologies: diode-connected HEMT, p-i-n diode, and nonlinear GaN mesa resistor. The RFIO PA with mesa resistor inphasing network achieves a linearity-efficiency compromise with −27.9 dBc adjacent channel leakage ratio (ACLR) and 29% PAE at an average output power of 27.7 dBm for a 100-MHz long-term evolution (LTE) signal with 7.9 dB peak-to-average power ratio (PAPR) centered at 10 GHz.

A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements

Outphasing Class-E power amplifiers (OEPAs) using isolating power combiners and an inverse cosine signal component separator are inherently linear but suffer from low efficiency at power back-off. For high efficiency both at maximum output power and at power back-off, non-isolating power combiners are required. In this brief the linearity of OEPAs using non-isolating power combiners is studied theoretically and validated by measurement of a 1.8 GHz 20 dBm OEPA implemented in a standard 65-nm CMOS technology using an off-chip transmission-line-based combiner. The developed theoretical model for the linearity is then employed to define digital pre-distortion (DPD) parameters for the implemented OEPA. Using this theory-based DPD and without any AM/AM and AM/PM characterizations, –31 dB RMS EVM level and below –30 dB ACLR were measured for a 13.1 dBm 6.25 MHz 30 Mbit/s 7 dB PAPR 64QAM signal with 41.8% drain efficiency and 33.6% power added efficiency.

Theory and Implementation of RF-Input <newline/>Outphasing Power Amplification

Conventional outphasing power amplifier systems require both a radio frequency (RF) carrier input and a separate baseband input to synthesize a modulated RF output. This work presents an RF-input/RF-output outphasing power amplifier that directly amplifies a modulated RF input, eliminating the need for multiple costly IQ modulators and baseband signal component separation as in previous outphasing systems. An RF signal decomposition network directly synthesizes the phase- and amplitude-modulated signals used to drive the branch power amplifiers (PAs). With this approach, a modulated RF signal including zero-crossings can be applied to the single RF input port of the outphasing RF amplifier system. The proposed technique is demonstrated at 2.14 GHz in a four-way lossless outphasing amplifier with transmission-line power combiner. The RF decomposition network is implemented using a transmission-line resistance compression network with nonlinear loads designed to provide the necessary amplitude and phase decomposition. The resulting proof-of-concept outphasing power amplifier has a peak CW output power of 93 W, peak drain efficiency of 70%, and performance on par with a previously-demonstrated outphasing and power combining system requiring four IQ modulators and a digital signal component separator.

High-Throughput Signal Component Separator for Asymmetric Multi-Level Outphasing Power Amplifiers

This paper presents an energy-efficient high-throughput and high-precision signal component separator (SCS) chip design for the asymmetric-multilevel-outphasing (AMO) power amplifier. It uses a fixed-point piece-wise linear functional approximation developed to improve the hardware efficiency of the outphasing signal processing functions. The chip is fabricated in 45 nm SOI CMOS process and the SCS consumes an active area of 1.5 mm2. The new algorithm enables the SCS to run at a throughput of 3.4 GSamples/s producing the phases with 12-bit accuracy. Compared to traditional low-throughput AMO SCS implementations, at 0.8 GSamples/s this design improves the area efficiency by 25× and the energy-efficiency by 2×. This fastest high-precision SCS to date enables a new class of high-throughput mm-wave and base station transmitters that can operate at high area, energy and spectral efficiency.

A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters

Linear amplification with nonlinear components (LINC) is an attractive technique for achieving linear amplification with high efficiency. This paper presents a sub-mW all-digital signal component separator (SCS) design for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. In addition, a digital mismatch compensation scheme is proposed and integrated into the SCS to reduce the design complexity of the power amplifier. This chip is manufactured in a 90 nm standard CMOS process with an active area of 0.06 mm2. The DCPS can generate phase-modulated signals at 100 MHz with 8-bit resolution and RMS error 9.33 ps (0.34°). The phase calculation can be performed at a maximum speed of 50 MHz using a 0.5 V supply voltage, resulting in a 73.88% power reduction. Comparing to state-of-the-art, the power consumption of the overall SCS is only 949.5 μW which minimizes the power overhead for an LINC transmitter. This SCS with the branch mismatch compensation provides a 0.02 dB gain and 0.15° phase fine-tune resolution without adding additional front-end circuits. Considering 1 dB gain and 10° phase mismatch, the system EVM of - 29.81 dB and ACPR of - 34.56 dB can still be achieved for 5 MHz bandwidth 64-QAM OFDM signals.

Highly efficient uneven multi-level LINC transmitter

To improve power efficiency in a transmitter, a novel method is proposed, this being an uneven multi-level linear amplifier with a nonlinear component (UMLINC). Compared to a normal multi-level LINC (MLINC), the UMLINC employs a new uneven multi-level signal component separator (UMSCS) that significantly improves transmitter efficiency.

Low-Power Signal Component Separator for a 64-QAM 802.11 LINC Transmitter

A LINC transmitter provides linear amplification while employing two nonlinear high-efficiency power amplifiers. This work proposes a LINC architecture where the two constant-envelope components of the signal are separated in the baseband analog domain. The signal component separator can achieve a power consumption which is significantly lower than conventional digital implementations. A signal component separator for 64-QAM 802.11a/g Wireless LANs is implemented in a 0.25- mum CMOS process, the circuit occupies less than 0.1 and consumes 45 mW from the 2.5-V supply. The measured EVM, ACPR, and alternate-ACPR of the recombined signal components are , and , respectively.

RF signal component separator for LINC transmitters

An experimental test bed of a novel full analogue microwave LINC signal component separator scheme is presented. The proposed experiment has been performed to validate the theory and to demonstrate the usefulness of the proposed solution, constituting the preliminary and mandatory step before a completely integrated version.

A Voltage-Translinear Based CMOS Signal Component Separator Chip for Linear LINC Transmitters

The LINC transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. One crucial signal processing function of LINC is the signal component separator (SCS) which forms two constant-amplitude phase-modulated signals from the source signal. This paper presents an analog SCS chip implemented in a 0.35 μm CMOS process using a novel design based on the so-called voltage-translinear circuit principle. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that all output spurious levels some -55{\rm dBc} and -48 dBc could be obtained with a North American Digital Cellular (NADC) signal and an IS-95 signal, respectively. This implies a high degree of linearity.

Low-memory digital signal component separator forLINC transmitters

Current digital implementations of the LINC transmitter's signal component separator use large two-dimensional lookup tables. The effects and benefits of using a smaller one-dimensional lookup table are discussed, and simulation results are given showing that the size of the lookup table can be reduced by several orders of magnitude without affecting the transmitter's linearity.

A 200-MHz IF BiCMOS signal component separator for linear LINC transmitters

The linear amplification with nonlinear components (LINC) transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. The signal component separator (SCS) is a crucial signal processing function of LINC. It forms two constant-amplitude phase-modulated signal components from the input signal. Due to the nonlinear signal processing involved, digital signal processing (DSP) implementation of the SCS at baseband has so far been assumed to be the best choice although it suffers from matching, bandwidth and power consumption problems. In this paper a new SCS architecture based on analog integrated circuit techniques is presented to avoid the disadvantages in a DSP based realization. A 200-MHz IF SCS chip using the proposed architecture was designed and fabricated in a 0.8 /spl mu/m BiCMOS process. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that spurious levels around -50 dBc could be obtained with a /spl pi//4-shifted DQPSK modulated North American Digital Cellular (NADC) signal. This implies a high degree of linearity in the implemented LINC transmitter.

Gain and phase error-free LINC transmitter

This paper presents a new correction technique for linear amplification with nonlinear component transmitters. During the transmit mode, the algorithm modulates and filters the baseband signal as a normal signal component separator, while during the correction mode, by use of a downconversion mixer, the gain and phase imbalance are measured and compensated by introducing a correction. This system is free of adjacent channel interference during the correction period. Analytical results and simulations demonstrate that this system is sufficient to suppress the out-of-band spectrum for mobile communications.

The effect of quantization in a digital signal component separator for LINC transmitters

Spectrally efficient modulation schemes have been chosen for the second generation of cellular systems in the United States and Japan, as well as for private mobile radio (PMR) systems. This paper analyzes the effect of quantization in a digital signal component separator (SCS) for linear amplification with nonlinear components (LINC) transmitters. The analysis relies on the fact that the two signal components can be obtained as the source signal plus/minus a signal in quadrature to the source signal. The equations derived are vital because they allow the designer to optimize digital signal processor (DSP) power consumption and bandwidth. The word lengths that are required for the source signal and the quadrature signal can be calculated from the amplifier gain characteristic, the probability density function for the modulation scheme, and the specified adjacent channel interference (ACI). The validity of the analysis has been verified by means of simulations.

Effects of reconstruction filters and sampling ratefor adigital signal component separator on LINC transmitter performance

The authors investigate how reconstruction filters and sampling rate for a digital signal component separator affect the performance of an LINC transmitter. A method is described that, for a specified adjacent channel interference level, finds a nearly optimal cutoff frequency for a given filter approximation and the minimum sampling rate.