SiGe Channel Devices Research Articles

Monte Carlo Analysis of -Type SiGe-Channel Nanosheet Performance

The performance of Si0.75Ge0.25-channel <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -type nanosheet (NS) devices with a gate length of 14 nm and a sheet width of 12 nm is investigated by Monte Carlo (MC) device simulation. It is found that the stress in the Si–Ge channel can eliminate the performance imbalance with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> -type NSs arising from the (001) surface in the absence of stress. The performance is the same as the theoretical performance of Si-channel (cSi) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -type NSs with Si0.5Ge0.5 source/drain (S/D) pockets under the ideal assumption that no stress relaxation, e.g., due to grain boundaries from merging epitaxial growth occurs for the cSi devices. It is shown that the performance levels can be related to stress-induced quasi-ballistic velocity overshoot and the impact of alloy scattering. This is not captured by standard drift–diffusion (DD) simulation where a smaller saturation velocity predicts a performance degradation for Si–Ge channel devices.

Investigation of degradation behavior under negative bias temperature stress in Si/Si0.8Ge0.2 metal-oxide-semiconductor capacitors

In this paper, capacitance and conductance characteristics are used to explain reliability issues in metal-oxide-semiconductor capacitors (MOSCAPs) with a silicon-germanium (SiGe) channel. The SiGe channel devices are also comprehensively compared to traditional Si channel devices. After negative bias temperature stress, both exhibit flat-band voltage (V FB) shifts in the negative direction and a rise in the conductance hump. Generally, the process of Si devices is more stable than SiGe devices, resulting in the interface quality of Si MOSCAPs being better due to lattice constant matching at the interface. However, it is noteworthy that the degradation of Si MOSCAPs is more serious than that of Side MOSCAPs. Therefore, this study quantitatively extracts the interface defects and illustrates the generation of interface defects with a reaction-diffusion model. In addition, the difference in the injected energy level is used to explain the difference in the VFB shift.

Hole Transport in Strained and Relaxed SiGe Channel Extremely Thin SOI MOSFETs

We report experimental data comparing aggressively scaled SiGe channel extremely thin SOI MOSFETs with either relaxed or strained channels. The analysis clearly demonstrates that without strain, SiGe channel delivers performance comparable with relaxed Si devices. Significantly higher performance is observed only in compressively strained SiGe channel devices, especially in narrower devices where the transverse component of the strain is partially relaxed.

PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD- $\hbox{SiN}_{x}$ Stressing Layer

In this letter, the SiGe-channel PMOS transistors integrated with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx stressing layer have been successfully fabricated. The performance improvements of devices with a gate length (Lg )of down to 40 nm were studied. For long-channel SiGe-channel PMOS, the mobility is at least 50% higher than that of the conventional bulk-Si PMOS. Moreover, compared to the conventional short-channel SiGe-channel devices, the highly compressive CESL stressor shows 32% current gain for Lg = 40 nm PMOS with the thinnest 9 A Si-cap. Therefore, integrating the stressed CESL technique into the SiGe-channel structure is an efficient method for improving PMOS device performance.

A First Principles Alloy Scattering Approach for Monte Carlo Hole Mobility Calculations

We present an ab-inito band-structure approach that can be applied for holes in Monte Carlo simulations of strained SiGe channel devices in order to remove the uncertainties of alloy scattering parameters along with addressing the effects of strain.

Low frequency noise in SiGe-base heterojunction bipolar transistors and SiGe-channel metal oxide semiconductor field effect transistors

We show that low frequency noise (LFN) in SiGe-base heterojunction bipolar transistors and SiGe-channel pMOSFETs may be made significantly lower than that in their all-Si counterparts and indicate how this can be done. Optimization of LFN in SiGe channel pMOSFETs follows from a calculation involving a novel analytical model, which accounts for both static and LFN characteristics of SiGe-channel devices.