Side-wall Technique Research Articles

Sidewalls and PVDs below embankments on soft soils – three-dimensional analysis by FEM

The sidewall technique (steel sheet pile or reinforced concrete walls, typically) – combined or not with prefabricated vertical drains (PVDs) – is a technique that minimizes the lateral deformation and upward displacement in the surrounding ground of embankments on soft soils, as well as increasing the overall stability of the structures. Although there is a large number of studies in the literature involving PVDs, there is a lack of studies regarding the sidewall solution, especially involving three-dimensional analysis. In order to overcome this deficiency, a computer code based on the finite element method (FEM) is used to analyse the three-dimensional behaviour of an embankment on soft soil incorporating sidewalls and PVDs. The same embankment, but without the vertical drains, is also modelled and compared with the case of PVDs. In addition, a parametric study is performed to evaluate the influence of the bending stiffness of the wall on the behaviour of the embankment. The computer code incorporates fully mechanical-hydraulic coupled analysis with the soil constitutive relations simulated by the p–q–θ critical state model.

The spike generator in the labellar taste receptors of the blowfly is differently affected by 4-aminopyridine and 5-hydroxytryptamine

In taste chemoreception of invertebrates the interaction of taste stimuli with specific membrane receptors and/or ion channels located in the apical membrane of taste receptor cells results in the generation of a receptor potential which, in turn, activates the ‘encoder’ region to produce action potentials which propagate to the CNS.This study investigates, in the labellar chemosensilla of the blowfly, Protophormia terraenovae, the voltage-gated K+ currents involved in the action potential repolarization and repetitive firing of the neurons by way of the Kv channel inhibitors, 4-aminopyridine and 5-hydroxytryptamine.The receptor potential and the spike activity were simultaneously recorded from the ‘salt’, ‘sugar’ and ‘deterrent’ cells, by means of the extracellular side-wall technique, in response to 150mM NaCl, 100mM sucrose and 1mM quinine HCl, before, 0÷10min after apical administration of 4-AP (0.01–10mM) or 5-HT (0.1–100mM).The results show that the receptor potential in all three cells is neither affected by 4-AP nor by 5-HT. Instead, spike activity is significantly decreased, by way of blocking different Kv channel types: an inactivating A-type K+ current (KA) modulating repetitive firing of the cells and responsible for the after hyperpolarization, and a sustained K+ current that resembles the delayed rectifier (DKR) and contributes to action potential repolarization.

Fabrication of single-electron tunneling transistors with an electrically formed Coulomb island in a silicon-on-insulator nanowire

For the purpose of controllable characteristics, silicon single-electron tunneling transistors with an electrically formed Coulomb island are proposed and fabricated on the basis of the sidewall process technique. The fabricated devices are based on a silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) field effect transistor with the depletion gate. The key fabrication technique consists of two sidewall process techniques. One is the patterning of a uniform SOI nanowire, and the other is the formation of n-doped polysilicon sidewall depletion gates. While the width of a Coulomb island is determined by the width of a SOI nanowire, its length is defined by the separation between two sidewall depletion gates which are formed by a conventional lithographic process combined with the second sidewall process. These sidewall techniques combine the conventional lithography and process technology, and guarantee the compatibility with complementary MOS process technology. Moreover, critical dimension depends not on the lithographical limit but on the controllability of chemical vapor deposition and reactive-ion etching. Very uniform weakly p-doped SOI nanowire defined by the sidewall technique effectively suppresses unintentional tunnel junctions formed by the fluctuation of the geometry or dopant in SOI nanowire, and the Coulomb island size dependence of the device characteristics confirms the good controllability. A voltage gain larger than one and the controllability of Coulomb oscillation peak position are also successfully demonstrated, which are essential conditions for the integration of a single-electron tunneling transistor circuit. Further miniaturization and optimization of the proposed device will make room temperature designable single-electron tunneling transistors possible in the foreseeable future.

Development of three-dimensional memory die stack packages using polymer insulated sidewall technique

A newly designed three dimensional (3-D) memory die stack package has been established, and the prototype of the 3-D package using mechanical dies has been successfully demonstrated. Fabrication processes of the 3-D package consist of: (1) wafer cutting into die segments; (2) die passivation including sidewall insulation; (3) via opening on the original I/O pads; (4) I/O redistribution from center pads to sidewall; (5) bare die stacking using polymer adhesive; (6) sidewall interconnection; and (7) solder balls attachment. There are several significant improvements in this new 3-D package design compared with the current 3-D package concept. The unique feature of this newly developed package is the sidewall insulation of dies prior to the I/O redistribution of dies, which produces (1) better chip-to-wafer yields and (2) significant process simplification during subsequent fabrication steps. According to this design, 100% of die yields on a conventional wafer design can be obtained without any neighboring die losses which usually occur during the I/O redistribution processes of conventional 3-D package design. Furthermore, the new 3-D package design can simplify the following processes such as I/O redistribution, sidewall insulation, sidewall interconnection, and package formation. It is proven that the mechanical integrity of the prototype 3-D stacked package meets requirements of the JEDEC Level III and 85/spl deg/C/85% test.

High aspect ratio hole filling by tungsten chemical vapor deposition combined with a silicon sidewall and barrier metal for multilevel interconnection

A newly developed processing for high aspect ratio hole filling by tungsten chemical vapor deposition, combined with a Si sidewall technique and resist etch back is proposed. A high aspect ratio hole (around 3) was completely filled with W and W-Si alloy without voids. It is also proposed to interpose a TiN/TiSi2 layer between W and Si, in order to suppress rapid silicidation of W at high temperatures above 800 °C. Silicidation rates for W/TiN/TiSi2/Si systems were 2–2.5 orders of magnitude lower than W/Si systems. Electrical contact resistivity was kept to be lower than 1×10−5 Ω cm2 even after 900 °C annealing by suppressing rapid silicidation of W.