Sidewall Polymer Research Articles

Comparative investigation of anisotropic etches for polysilicon nanowire definition in thin film technology

We report a low-cost mass manufacturable route for polysilicon nanowire (NW) fabrication through comparative investigations of spacer etch techniques to realize nanowires from amorphous silicon (α-Si) layer. The process uses thin film technology and mature top-down microelectronics (linewidth > 10 μm). Anisotropic deep silicon etch process using the elevated plasma density of high-density low-pressure systems (HDLP) with a simultaneous flow of etchant SF6 and inhibitor C4F8 delivered nanowires with quarter circle shape. The nanowires are also characterised with significant sidewall striations and noticeable aggregation of polymers. HDLP etch system with a sequential flow of etchant SF6 and inhibitor C4F8 delivered a near rectangular nanowire shape. However, the generally good profile is marred with significant sidewall striations and accumulation of polymers at the tip of the etched sidewall. Shallow etch process using low density plasma in a cheap capacitively coupled reactive ion etch (RIE) equipment with a simultaneous flow of etchant SF6 and inhibitor O2 delivered nanowires with ideal rectangular shape. The nanowires have hardly visible sidewall striations and/or polymer. These results indicate that deep silicon HDLP etch processes albeit advanced and costly are not suitable for good quality nanowire definition using spacer etch from a thin film of α-Si layer. Low density plasma process with simultaneous flow of SF6 and O2 gases in relatively cheap RIE system provides high quality nanowires and hence, provides a simple, low cost, wafer scale mass manufacturable route for high quality polysilicon nanowire fabrication.

Directed Self-Assembly of Topological Defects of Liquid Crystals.

One of the alluring aspects of liquid crystals (LCs) is their readily controllable self-assembly behavior, leading to comprehension of complex topological structures and practical patterning applications. Here, we report on manipulating various kinds of topological defects by adopting an imprinted polymer-based soft microchannel that simultaneously imposes adjustable surface anchoring, confinement, and uniaxial alignment. Distinctive molecular orientation could be achieved by varying the surface anchoring conditions at the sidewall polymer and the rubbing directions on the bottom layer. On this pioneering platform, a common LC material, 8CB (4'-n-octyl-4-cyano-biphenyl), was placed where various topological defect domains were generated in a periodic arrangement. The experimental results showed that our platform can change the packing behavior and even the shape of topological defects by varying the rubbing condition. We believe that this facile tool to modulate surface boundary conditions combined with topographic confinement can open a way to use LC materials in potential optical and patterning applications.

Post Etch Residue Removal and Material Compatibility in BEOL Using Formulated Chemistries

A possible way to realize a 22.5 nm 1⁄2 pitch and beyond BEOL interconnect structures within the low-kmaterial is the partial-trench via first with self-aligned double patterning (SADP) integration approach. A scheme of this BEOL integration stack with the different materials used after patterning is described in Figure 1. In BEOL processing, fluorocarbon-containing plasma is commonly used to pattern silica-based dielectric layers. During the patterning of the low-kdielectric layer, a thin layer of fluoropolymer (CFx-type residues) is intentionally deposited on the dielectric sidewalls and TiN hardmask to ensure anisotropic etching and prevent/minimize dielectric degradation. This polymer layer must be removed from the sidewall and the via bottom prior to the subsequent processing steps to achieve good adhesion and coverage of materials deposited in the etched features. The compatibility requirement is even more stringent for advanced low-kdielectrics, i.e. materials with lowerk-value and higher porosity. The post etch residue (PER) amount and properties are specific and depend on the stack structure and the plasma that is used for patterning. The low-kmaterials and hardmasks that are used in this work are respectively an organo-silicate glass (OSG) type of low-kmaterial withk= 2.4 (~20 % open porosity) and low-stress TiN. Recent results clearly showed the presence of a highly fluorinated layer deposited on the trench sidewalls during the plasma etch based on a fluorocarbon plasma [1-3]. Commodity aqueous cleaning solutions, such as diluted HF, do not efficiently remove the sidewall polymers without etching the underlying layer (lift-off). Therefore, there is a need for commercially available chemicals that can be easily tuned to deal with the different requirements. This study focuses on the use of FOTOPUR® R 2300 mixed with H2O2 for polymer residue removal selectively to other materials (presented in the stack) such as MHM, metals (Cu, W), and porous low-k dielectrics. We will show that TiN etch can be easily tuned by changing the concentration of H2O2.

Efficient TSV Resist and Residue Removal in 3DIC

The continuing challenge to meet the need for lighter, smaller, faster and smarter electronic systems has pushed the advancement of 2.5D and 3D technology. The ability to create and integrate through-silicon vias (TSV) into device designs in 2.5- and 3-D platforms allows a decrease in interconnection path length, which results in improved device performance and reliability in a small form factor. Mainly due to its high silicon etch rate and selectivity to mask materials, the Bosch process is often used in the TSV fabrication. In this process, the silicon via is created by the deep reactive ion etching (DRIE). DRIE is comprised of repeating a combination of steps: an etch step and a passivation step. The passivation created in the DRIE process results in a fluoropolymer residue remaining on the wafer at the end of the process. The residue must be removed to enable deposition of a defect-free barrier, which enables a defect-free seed layer and void-free plating into the via. There are numerous technical papers and presentations on the etching and filling of these vias but the process for cleaning remains under addressed. Initially, standard processes used after RIE and consisting of an ashing process to remove any remaining photoresist, followed by immersion in a solution-based post etch residue remover were adopted for post-TSV cleans. However, the fluoropolymer does not have the same chemical characteristics as typical post-RIE etch residues and the major challenge has been the difficulty to completely remove it, especially on the via sidewall, using traditional post etches residue removers. Therefore, new formulated cleaning solutions and processes are actively sought for the removal of post etch residue for TSVs. This paper will describe a robust cleaning process for one step removal of both the photoresist and sidewall polymer residues from TSVs. A combination soak and high pressure spray process using a proprietary environmentally friendly chemistry, coupled with a megasonic final rinse provides a unique solution for both polymer residue and photoresist removals on high aspect ratio vias. SEM, EDX and Auger analysis will illustrate the cleanliness levels achieved.

A study of the mechanisms causing surface defects on sidewalls during Si etching for TSV (through Si via)

In this paper we report three mechanisms causing surface defects on Si sidewalls during Si etching for TSV. The first mechanism causing surface defects was a downward surface-defect formation due to the participation of the residual polymerizing gas in the transition periods between passivation steps and etch steps. The second mechanism was an upward surface-defect formation due to etchant attacking the interface between the Si and the sidewall polymer. Although the sidewall polymer was thick enough to protect the Si surface, it was not possible to avoid surface defects if the etch step was not switched to the following passivation step in time. The third mechanism was a sponge-like surface-defect formation caused by either poor polymer depositions or voids inside the sidewall polymer. The sponge-like surface defects were formed by Si isotropic etching through the weak points of the sidewall polymer. All three surface defects were considered as the major factors on TSV integration and packaging reliability issues.

Unique Size-Dependent Challenges for BEOL Cleans in the Patterning of Sub-20 nm Features

BEOL Cleans has been and continues to be one of the most mysterious black boxes of semiconductor manufacturing. It has the unenviable task of removing post-plasma processing polymer residues, being compatible with ultra low-k dielectric materials that continue to scale k-value at the expense of material strength, and ensuring that any formulation that accomplishes the above objectives is also compatible with Cu and all other metals on the wafer used for liners or caps. In order to meet the performance requirements of next generation devices, Moore's law mandates continued scaling of dimensions with the additional challenges of size-dependent complexities for BEOL cleans development. Patterning of sub-20 nm features on thin ILD stacks suffers from the problems of etch-induced line undulation [1, 2] and cleans-induced pattern collapse [3]. High aspect ratio's, non-uniform drying, surface tension and low material strength have all been implicated as the root cause for pattern collapse during cleans [4]. Classical equations used to describe pattern collapse for resist lines that rely on 2D beam theory and finite element modeling [5] are not as applicable to patterned low-k dielectrics because material changes such as sidewall polymer residues, lowering of Young's modulus and changing pattern densities present different solid surfaces with widely varying wettability and diffusivity parameters [6, .

Modification of Post-Etch Residues by UV for Wet Removal

In back-end of line processing, the polymer deposited on the dielectric sidewalls during the etch must be removed prior to subsequent processing steps to achieve high adhesion and good coverage of materials deposited in the etched features [1,. Typically, this is done by a combination of short plasma treatment and diluted wet clean, or by wet cleans alone. On the one hand, for porous dielectric stacks, a mild plasma treatment that preserves the integrity of the low-k dielectrics would not be sufficient to efficiently remove this residue. Furthermore, aqueous cleaning solutions is not efficient to achieve a complete removal without etching the underlying layer. Hence appropriate wet clean chemistries are needed to dissolve/decompose these polymers without etching the dielectric. On the other hand, analytical techniques available for direct characterization of sidewall polymer are limited. For a fast screening of potential chemistries capable of dissolving/removing polymer residues generated during the low-k etch, a fluoropolymer deposited on a blanket, checkerboard low-k substrate was used as a model polymer. In our recent study [, using X-ray photoelectron spectroscopy (XPS), it was shown that the polymer was composed of CF, CF2, and CF3 groups. This model polymer was found to be very similar to the polymer residue generated during the etch of the low-k stack using similar plasma. The present study mainly focused on the effect of UV treatment and the concentration of active component in wet clean solution on the structure change of the polymer and the enhancement of polymer removal.

TSV Resist and Residue Removal

3D integration is the most active methodology for increasing device performance. The ability to create Through Silicon Vias (TSV) provides the shortest path for interconnections and will result in increased device speed and reduced package footprint. There are numerous technical papers and presentations on the etching and filling of these vias, however the process for cleaning is seldom mentioned. Historically, after reactive ion etching (RIE), cleaning is accomplished using an ashing process to remove any remaining photoresist, followed by dipping the wafer in a solution-based post etch residue remover. However, in the case of TSV formation, deep reactive ion etching (DRIE) is used to create the vias. A byproduct of this etching process is the formation of a fluorinated passivation layer, often referred to as a fluoropolymer. The fluoropolymer is not easily removed using traditional post etch residue removers, thus creating the opportunity for new and improved formulations and processes for its removal. This paper will describe a robust cleaning process for one step removal of both the photoresist and sidewall polymer residues from TSVs. A combination soak and high pressure spray process using Dynastrip™ AP7880™-C, coupled with a megasonic final rinse provides clean results for high aspect ratio vias. SEM, EDX and Auger analysis will illustrate the cleanliness levels achieved.

X-ray fabrication of SAW resonators with narrow electrodes in thick high-aspect-ratio polymer templates

X-ray lithography shadow projection using silicon nitride-based x-ray masks is used to fabricate sub-micron scale, high-aspect-ratio structures in thick polymer templates for surface acoustic wave (SAW) applications. Interdigital electrode patterns with 380 nm wide, free-standing polymer features are fabricated in 2 µm thick templates, representing an aspect ratio of 5.26:1. The tall and narrow polymer ‘ribbons’ run laterally in a serpentine arrangement of 114 electrodes over a large area of approximately 30 µm × 250 µm. Aluminum deposition and lift-off using the polymer templates are performed to construct metal electrodes for the verification of SAW resonator performance above 2.5 GHz. Environmental scanning electron microscopy and atomic force microscopy are used to inspect the metal electrode edge and surface topology, and demonstrate the feasibility of metal lift-off with highly vertical sidewall polymer templates for SAW applications. Such precise polymer templates could offer interesting possibilities for acoustic applications requiring thick and/or narrow electrodes and reflectors not only through more traditional metal deposition approaches but also as thick etch masks for metal removal.

The Impact of Dielectric Films and Post-Metal Etch Wet Treatment on Charge-Induced Corrosion of Tungsten Vias

ABSTRACTThe prevention of charge-induced corrosion of tungsten vias after metal etch has been stud-ied with several types of commonly used wet chemical solutions and two kinds of dielectric film materials, silicon dioxide and silicon oxynitride. It was found that one of the solutions, leaving essentially no polymer residue on metal lines, could effectively prevent corrosion of tungsten vias. Other solutions either produced minor residues or severe sidewall erosion on metal lines. This study has shown that the combination of wet treatment with oxynitride as the dielectric charge shielding film was as effective as other conventional methods for preventing tungsten vias corrosion. However, for metal lines capped with silicon dioxide, significant sidewall ero-sion, surface roughness, and polymer residue were observed. Chemical reaction mechanisms are proposed for the preservation of tungsten vias after metal etch.

Sidewall damage in silica-based low- k material induced by different patterning plasma processes studied by energy filtered and analytical scanning TEM

The capabilities of energy filtered TEM and EELS/EDS in STEM mode are studied in order to determine the thickness and composition of the sidewall damage layer induced by different plasma patterning processes on a silica-based (SiOC:H) porous material. Concentration profiles are calculated from the obtained energy filtered elemental maps. The sidewall damage layer, typically less than 20 nm thick, has a lower carbon content than the bulk of the low- k layer what leads to an increase of the interline capacitance. In addition to the damage layer, a few nanometers thick carbon rich sidewall polymer layer is observed for some patterning plasma processes. Moreover the bulk composition of the porous low- k layer depends slightly on the used plasma process indicating that not only the sidewalls but also the low- k layer bulk is affected by the process.

Fabrication of sub-60-nm contact holes in silicon dioxide layers

We have developed a fabrication technique, comprising electron-beam writing, chemical shrinking, and silicon dioxide etching, for the fabrication of sub-60-nm contact holes. The dimensions of the contact holes after the electron-beam writing, chemical shrinkage, and plasma etching steps were 140, 93, and 53 nm, respectively. We carefully evaluated the critical process parameters, such as mixing-bake temperature, mixing-bake time, plasma etch selectivity, and the profile shapes. A higher mixing-bake temperature led to an overhang of the contact hole in the resist; the optimal mixing-bake conditions occur when heating at 110 °C for 70 s. A fluorinated mixture of gases (CHF3/CF4=1:1) was used to etch the nano-scale contact holes in the silicon dioxide layer. The formation of side-wall polymers during the plasma etch phase contributed further to the contact hole shrinkage in addition to resist chemical shrinkage. The ratio of the hole's perimeter to its area affects the shrinkage dimensions of the etch process, especially for smaller contact holes. The pattern reduction due to side-wall polymer deposition in etch process has the inverse relationship with the diameter of contact hole.

Removal of the Metallorganic Polymer Residues Formed at Via Holes

The removal characteristics of polymer layers formed during the reactive ion etching of via holes with via etch-stopped on a TiN layer (VEST) structure were investigated under various ashing and stripping conditions. A relatively thick sidewall polymer layer containing large amounts of F and Ti due to the reaction between -based etching gas and a sputtered Ti layer were observed, while a comparatively thin polymer layer with negligible F and only a small amount of Ti was formed at the bottom of the via hole. The intruded sunflower-shaped thick polymer layer at the boundary of the via hole was clearly distinguishable after ashing under various conditions. Oxygen-based plasma ashing removed F-containing carbon contaminants but left the metallorganic polymer due to the formation of metal oxides such as Additional wet stripping is required to completely remove the metallorganic polymer residues. Nonhydroxylamine (non-HA)-based strippers more effectively removed the polymer layer than HA-based strippers, regardless of the photoresist used. Polymer hardening due to the ashing at elevated temperatures reduced the wet stripping capability. This study shows that a polymer-free via hole can be achieved by using a non-HA-based stripper and Ar dry cleaning and by keeping the ashing temperature low enough to prevent polymer hardening. © 2004 The Electrochemical Society. All rights reserved.

Fabrication of sub-60-nm contact holes in silicon dioxide layers

We have developed a fabrication technique, comprising electron-beam writing, chemical shrinking, and silicon dioxide etching, for the fabrication of sub-60-nm contact holes. The dimensions of the contact holes after the electron-beam writing, chemical shrinkage, and plasma etching steps were 140, 93, and 53 nm, respectively. We carefully evaluated the critical process parameters, such as mixing-bake temperature, mixing-bake time, plasma etch selectivity, and the profile shapes. A higher mixing-bake temperature led to an overhang of the contact hole in the resist; the optimal mixing-bake conditions occur when heating at 110 °C for 70 s. A fluorinated mixture of gases (CHF 3/CF 4=1:1) was used to etch the nano-scale contact holes in the silicon dioxide layer. The formation of side-wall polymers during the plasma etch phase contributed further to the contact hole shrinkage in addition to resist chemical shrinkage. The ratio of the hole's perimeter to its area affects the shrinkage dimensions of the etch process, especially for smaller contact holes. The pattern reduction due to side-wall polymer deposition in etch process has the inverse relationship with the diameter of contact hole.

Removal of the Polymer Formed at Via Hole with Via Etching Stopped on an Al layer Structure

We examined and analyzed the removal characteristics of polymer layers which were formed during the reactive ion etching (RIE) of via holes with via etching stopped on an Al layer (VESA) structure under various ashing and stripping conditions. Double metalorganic polymer layers, with and without F, were formed at the bottom of the via hole while only a homogeneous single metalorganic polymer layer with F was observed at the sidewall. The photoresist layer was almost completely removed by oxygen-based plasma ashing, while the metalorganic polymer layers containing F formed during RIE process remained. Nonuniform metal gap filling due to the residual sidewall polymer caused increased resistance due to the formation of voids at via metal lines. An additional wet stripping process was required to completely remove the sidewall polymer and to realize uniform metal gap filling. Wet stripping efficiency increased as the ashing temperature was lowered. A non-hydroxylamine (non-HA) based stripper removed the RIE-induced polymer more effectively than a HA based stripper regardless of the photoresist used. This study reveals that it is necessary to reduce the hardening of the polymer layer by lowering the ashing temperatures and to use a non-HA based stripper to realize reliable metal gap filling at via holes.

A global evaluation of stripping efficiency by TD-GCMS

In this work, a global evaluation of stripping efficiency and resist poisoning by TD-GCMS is proposed. It is shown that TD-GCMS is very sensitive to post stripping residues: photoresist mainly and in a less extend sidewall polymers. This method allows the quantification of the stripping efficiency in the 99.99% range. TD-GCMS also offers a sensitive detection of the organic contamination left by the BEOL wet stripping responsible of resist poisoning: traces of solvent trapped in porous material.

Effect of de-ionized water parameters rinse on postmetal etch residue removal using semiaqueous cleaning chemistries

As the plasma etch processes have evolved, the wet cleaning process has included resist stripping, sidewall polymer removal, and also encompasses surface cleaning, which can include mobile ion reduction and damaged metal removal. This scenario has ushered in the recent popularity of fluoride based semiaqueous cleaning (SAC™) chemistries for postmetal etch cleaning. These chemicals can include low or room temperature operation and very short process times, are easily rinseable in water, and are easy to dispose of. This study looks at the effects of cleaning metal and via structures with SAC™ chemistries. The primary focus is on metal integrity when looking at: (1) process latitude of the cleaning chemicals; (2) the effect of de-ionized water rinsing; and (3) the effect of utilizing different intermediate rinses. This study shows that an emphasis should now be placed on total process optimization. This not only includes the cleaning chemistry, but also the rinsing process, which had historically not been a focus item.

Plasma etch/deposition modeling: A new dynamically coupled multiscale code and comparison with experiment

Next-generation plasma-process modeling tools can provide new insight into process dynamics by resolving the diverse length and time scales present in reactor systems. The length scales range from the size of the reactor (∼10 cm) to surface details (∼100 nm), and time scales from electron sheath-transit times (nanoseconds) to total process time (minutes). Other key features include dynamic coupling of the plasma and solid (particles and fields), and the ability to model realistic surface interactions (deposition, etch, sputter, polymerization, etc.). A computational tool has been developed which provides all of these features through the coupling of heterogeneous code modules [hybrid plasma, particle in cell (PIC) plasma and solid surface chemistry] and through time-sampling techniques. The hybrid code (particle ions, fluid electrons) provides the basis for modeling the large-scale plasma reactor using a finite-element mesh to represent complex reactor geometries. The PIC code is used in the dynamic sheath boundary region to account for electron movement. The solid surface chemistry code is specially developed to model complex interactions between surface mechanisms, such as the formation of polymer and its possible removal by high-energy particles. The solid surface module uses a finite element scheme with adaptive mesh refinement (on a many-cycle time scale) to follow the complex surface evolution. These code modules exchange information on a sub-rf-period timescale, allowing for direct solid/plasma interactions. The long process times (minutes) are simulated by result sampling and using the slow evolution of the plasma/solid system. The code also performs surface charge migration and local gas heating to more completely represent the physical processes occurring in a plasma processing operation. The modeling of plasma processing must also account for the multilayer films and many species of particles and material types. The incorporation of this information in the simulations has demonstrated mask erosion. The simulations performed using this code have also shown good correlation to experimental results for steady state etch rates, etch rates as a function of via size, sidewall polymer evolution, and the production of “sputter wind” and surface charging. In deposition mode, the simulations demonstrate the experimentally observed polymer and deposited film topology.

Chemical and Electrical Characterization of the Interaction of BCl3 / Cl2 Etching and CF 4 / H 2 O Stripping Plasmas with Aluminum Surfaces

In this work, the effect of etching and stripping plasmas on Al surfaces during patterning is investigated. The purpose is to consider the direct impact of plasma exposure on the intrinsic electrical properties of the interconnect in terms of its effectively conductive cross section. First, the origin of the plasma‐transformed sidewall area is clarified. It is demonstrated by X‐ray photoelectron spectroscopy that after the final dry stripping sequence, the Al sidewalls are transformed into or due to the chemical interaction with the plasma, which degrades their metallic, conductive nature. The actual dimension of the plasma‐affected region is then quantified electrically to be in the order of 20 nm and is found to increase with decreasing ratio. The latter indicates that it is the structural integrity of the protecting sidewall polymer formed during the etching process which controls the degree of interaction between the interconnect sidewall and the subsequent stripping plasma. Since the plasma interaction seriously degrades the electrical performance of an Al interconnect by reducing its effective conductive area, care should be taken in general that while optimizing a plasma‐stripping sequence, both stripping efficiency and sidewall interaction are considered. © 1999 The Electrochemical Society. All rights reserved.

Analyses of Post Metal Etch Cleaning in Downstream H 2 O ‐ Based Plasma Followed by a Wet Chemistry

The evolution of surface chemical species on etched Al (Cu) lines and films has been investigated by X‐ray photoelectron spectroscopy in a postetch cleaning process, with the aim of understanding the role of each step on the removal of the etching residues.The results from the in situ strip in downstream plasma show that most of the organic species are removed by oxidation reactions, together with the majority of the Cl species. However, the sidewall polymer leaves a Cl‐containing residual film due to its high metallic content and oxidation reactions. Adding a small amount of to the plasma can have some advantages mainly making the residues more water soluble. Further ex situ wet chemical treatment is needed to remove the oxide/fluoride layer formed in the in situ step. It is argued that a clean surface, consisting of Al bonded strongly to its native oxide, is essential to the reliability of the interconnect. It is also found that after dry etching there are two kinds of Cu species present at the Al surface layers. One is a residue, which can be removed effectively by the cleaning. The other is elemental Cu enrichment. Rutherford backscattering spectrometry results reveal that this enrichment distributes over a depth of about 40 nm in Al, with a peak concentration of two to three times the bulk value. © 1999 The Electrochemical Society. All rights reserved.