SiC MOSFET Research Articles

Comparison of total ionizing dose effects in SiC MOSFETs with double trench versus asymmetric trench

Comparison of total ionizing dose effects in SiC MOSFETs with double trench versus asymmetric trench

Degradation Under Low Drain Bias Induced by Heavy Ion in SiC MOSFETs

Degradation Under Low Drain Bias Induced by Heavy Ion in SiC MOSFETs

Accurate Evaluation of Threshold Voltage Hysteresis in SiC MOSFET Under Switching Stress

Accurate Evaluation of Threshold Voltage Hysteresis in SiC MOSFET Under Switching Stress

Comparative Investigation on Ionizing Irradiation- Induced Threshold Voltage Degradation for 1200-V DT SiC MOSFET by Experiment and Simulation

Comparative Investigation on Ionizing Irradiation- Induced Threshold Voltage Degradation for 1200-V DT SiC MOSFET by Experiment and Simulation

Suppression Effect of Split-Gate Structure on Repetitive Avalanche Stress Induced Degradation for SiC MOSFETs

Suppression Effect of Split-Gate Structure on Repetitive Avalanche Stress Induced Degradation for SiC MOSFETs

Short-Circuit Dynamic Model of SiC MOSFET Considering Failure Modes

Short-Circuit Dynamic Model of SiC MOSFET Considering Failure Modes

A Quasi-Floating Channel-Based SPICE Model for Improving the Modeling Accuracy of SiC MOSFETs With Multiple Device Structures

A Quasi-Floating Channel-Based SPICE Model for Improving the Modeling Accuracy of SiC MOSFETs With Multiple Device Structures

Characteristics of a 1200 V Hybrid Power Switch Comprising a Si IGBT and a SiC MOSFET

Hybrid Power Switches (HPS) combine the advantages of SiC unipolar and Si bipolar devices and therefore can bridge the gap between these technologies. In this paper, the performance of a hybrid power switch configuration based on the latest SiC MOSFET and Si IGBT technologies is presented. The device is evaluated through experimental measurements of its characteristics under various conditions. The results show the HPS can achieve switching losses as low as a SiC MOSFET while offering the high current capability of the IGBT without significant increase in costs.

Measurement of half-bridge parasitic impedances using a flexible test probe

The use of SiC MOSFETs in power applications allows to increase power density and efficiency because switching frequencies are higher. However, parasitic impedances are responsible for oscillations that can have negative effects. In this paper we analyse the parasitic impedances of a half-bridge formed by a busbar PCB laminated with SiC MOSFETs. Using the distributed parameter approach, we have developed a procedure to characterize the impedance of the switching current loop responsible for the oscillations in the switching. According to the above, the conclusions obtained will be presented.

Study on the influence mechanism of gate oxide degradation on DM EMI signals in SiC MOSFET

This paper investigates gate oxide degradation and its influence on Differential Mode(DM) EMI signals. The study reveals that changes in the parasitic capacitance within the chip, resulting from gate oxide degradation, can modify the amplitude-frequency characteristics of DM EMI signals, leading to unexpected transmission outcomes. This paper subjects SiC MOSFET modules to periodic high-temperature gate bias stress, extracts the spectrum characteristics of DM EMI, and assesses the impact of junction temperature. The analysis explores the impact of gate oxide degradation on low and high frequency DM EMI signals. Experimental results reveal distinct sensitivities of amplitude-frequency characteristics in the DM EMI signals to temperature variations and responses to gate oxide degradation at various frequency bands. The extrapolation of the correlation between the frequency-domain characteristics of the DM EMI signals and the degree of gate oxide degradation introduces a novel approach to evaluate the lifespan of power electronic devices.

High-temperature time-dependent dielectric breakdown of 4H-SiC MOS capacitors

—With the rapid applications of silicon carbide metal–oxide–semiconductor field-effect transistor (SiC MOSFET) power devices, further improving the performance of SiC MOSFET device through enhancing its gate oxide reliability is one of the crucial directions. The density of interface states in a SiC MOSFET is a significant parameter that affects the reliability of the gate oxide layer. In this paper, the SiC MOS capacitors (MOSCAPs) were prepared by the 1250 °C dry oxidation and 1350 °C NO annealing process. Then, we analyzed the mechanisms of the breakdown by two group of ramped experiment. And we still evaluated the reliability of oxide layer via the high-temperature time-dependent dielectric breakdown (TDDB) tests on the prepared MOSCAPs, meanwhile, the temperature effect on the reliability was considered. Furthermore, the E, 1/E, and E models with Weibull plotting were used to calculate the tBD lifetimes and failure analysis was carried on the failed samples finally. The results indicate that: (1) the impact of the generation and accumulation of the traps in the oxide, which is the main mechanisms of device failure; (2) The prediction of lifetime was calculated with three models at different acceleration factors; (3) at high-temperature, although the lower the density of interface states is, the Si epitaxial growth and C cluster will manifest in the oxide surface and lead to the breakdown of SiC MOSCAPs.

Asymmetric trench SiC MOSFET with integrated channel accumulation diode for enhanced reverse conduction and switching characteristics

A novel asymmetric trench Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor (SiC MOSFET), featuring an integrated channel accumulation diode (CAD-MOS), has been proposed and investigated through numerical simulation. This innovative design aims to mitigate switching losses and eliminate the bipolar degradation of the body diode. The current spreading layer (CSL) channel, strategically positioned in the centre of the dummy gate, offers a low-barrier reverse conduction path. This represents a substantial advancement over the traditional PN body diode, significantly reducing the reverse conduction voltage drop from 2.84 V in the PN body diode to a mere 1.39 V in the CAD-MOS. Meanwhile, the reverse recovery charge of the CAD-MOS is reduced to 0.95 μC/cm2, and the peak reverse recovery current stands at 45 A/cm2. Compared to conventional asymmetrical trench SiC MOSFET (CON-MOS), the CAD-MOS exhibits a 68.1 % reduction in reverse recovery charge and a 63.4 % decrease in peak reverse recovery current. The split-gate design also reduces the device gate to source capacitance (CGS), resulting in a 17.4 % reduction in total switching losses to 3.64 mJ/cm2. CAD-MOS also exhibits a reduced gate turn-on charge and demonstrates an enhancement in high-frequency figure of merit (HF-FOM) by 8.1 %.

Modeling of the Influence on Effective VTH From Interface States, Short Channel Effects, and Contact Resistance in SiC MOSFETs

Modeling of the Influence on Effective <i>V</i>TH From Interface States, Short Channel Effects, and Contact Resistance in SiC MOSFETs

Junction Temperature Correction Method for SiC MOSFET Based on Turn-Off Oscillation Frequency of Drain-Source Voltage

Junction Temperature Correction Method for SiC MOSFET Based on Turn-Off Oscillation Frequency of Drain-Source Voltage

An Online Junction Temperature Estimating Method for SiC MOSFETs Based on Steady-State Features and GPR

An Online Junction Temperature Estimating Method for SiC MOSFETs Based on Steady-State Features and GPR

A Cost-Efficient Active Gate Driver for Seamless Slew Rate Control of SiC MOSFETs

A Cost-Efficient Active Gate Driver for Seamless Slew Rate Control of SiC MOSFETs

Failure Mechanism Analysis of 1.2 kV SiC MOSFETs Under Low-Temperature Storage, Power Cycling, and Short-Circuit Interactions

Failure Mechanism Analysis of 1.2 kV SiC MOSFETs Under Low-Temperature Storage, Power Cycling, and Short-Circuit Interactions

A Gate Degradation Independent Online Junction Temperature Estimation Method for SiC MOSFETs Based on Residual Resistance

A Gate Degradation Independent Online Junction Temperature Estimation Method for SiC MOSFETs Based on Residual Resistance

A Control Strategy for Reducing Voltage Ripples in Series-Connected SiC MOSFETs Using Active Clamping Modules in High Power VSCs

A Control Strategy for Reducing Voltage Ripples in Series-Connected SiC MOSFETs Using Active Clamping Modules in High Power VSCs

A Dynamic Current Balancing Method for Paralleled SiC MOSFETs With Gate-Branch Full-Coupled Inductors

A Dynamic Current Balancing Method for Paralleled SiC MOSFETs With Gate-Branch Full-Coupled Inductors