Si Virtual Substrates Research Articles

Thinned GaInP/GaInAs/Ge solar cells grown with reduced cracking on Ge|Si virtual substrates

Reducing the formation of cracks during growth of GaInP/GaInAs/Ge 3-junction solar cells on Ge|Si virtual substrates has been attempted by thinning the structure, namely the Ge bottom cell and the GaInAs middle cell. The theoretical analysis performed using realistic device parameters indicates that the GaInAs middle cell can be drastically thinned to 1000 nm while increasing its In content to 8% with an efficiency loss in the 3-junction cell below 3%. The experimental results show that the formation of macroscopic cracks is prevented in thinned GaInAs/Ge 2-junction and GaInP/GaInAs/Ge 3-junction cells. These prototype crack-free multijunction cells demonstrate the concept and were used to rule out any possible component integration issue. The performance metrics are limited by the high threading dislocation density over 2·107cm−2 in the virtual substrates used, but an almost current matched, crack-free, thinned 3-junction solar cell is demonstrated, and the pathway towards solar cells with higher voltages identified.

Ge growth on porous silicon: The effect of buffer porosity on the epilayer crystalline quality

We report on the epitaxial growth of Ge virtual substrates directly on Si (001) and on different porosity porous silicon (pSi) buffers. Obtained results indicate that Ge grown on low porosity (22%) pSi buffer has a better crystalline quality compared to Ge grown on bulk Si and on higher porosity buffers. This result is attributed to the compliant nature of pSi and to its reduced Young's modulus, which leads to plastic tensile deformation of the 22% porosity buffer under the in-plane tensile stress introduced by Ge lattice. The same result is not observed for higher porosity buffers, this effect being attributed to the higher buffer fragility. A low porosity pSi layer can hence be used as buffer for the growth of Ge on Si virtual substrates with reduced dislocation content and for the growth of Ge based devices or the successive integration of III-V semiconductors on Si.

Epitaxy of In0.01Ga0.99As on Ge/offcut Si (001) virtual substrate

In0.01Ga0.99As thin films free of anti-phase domains were grown on 7° offcut Si (001) substrates using Ge as buffer layers. The Ge layers were grown by ultrahigh vacuum chemical vapor deposition using ‘low/high temperature’ two-step strategy, while the In0.01Ga0.99As layers were grown by metal-organic chemical vapor deposition. The etch-pit counting, cross-section and plane-view transmission electron microscopy, room temperature photoluminescence measurements are performed to study the dependence of In0.01Ga0.99As quality on the thickness of Ge buffer. The threading dislocation density of Ge layer was found to be inversely proportional to the square root of its thickness. The threading dislocation density of In0.01Ga0.99As on 300nm thick Ge/offcut Si was about 4×108cm−2. Higher quality In0.01Ga0.99As can be obtained on thicker Ge/offcut Si virtual substrate. We found that the threading dislocations acted as non-radiative recombination centers and deteriorated the luminescence of In0.01Ga0.99As remarkably. Secondary ion mass spectrometry measurement indicated as low as 1016cm−3 Ge unintended doping in In0.01Ga0.99As.

Molecular-beam epitaxial growth of III–V semiconductors on Ge∕Si for metal-oxide-semiconductor device fabrication

We describe the fabrication of III–V metal-oxide-semiconductor (MOS) devices on Ge∕Si virtual substrates using molecular-beam epitaxy. Migration-enhanced epitaxy and low temperature normal GaAs growth produced a sufficiently smooth surface to deposit gate oxides. A 300nm thick GaAs buffer layer was grown, followed by a 10nm growth of In0.2Ga0.8As high mobility channel layer. An 8.5nm thick Al2O3 layer was deposited ex situ by atomic-layer deposition. Capacitance-voltage (C-V) characteristics show the unpinning of Fermi level. This work suggests this materials combination as a promising candidate for the design of advanced, nonclassical complementary MOS and optoelectronic devices on Si substrates.

III-V Device Integration on Silicon Via Metamorphic SiGe Substrates

A range of high performance minority carrier devices have been successfully fabricated on Si virtual substrates where threading dislocation densities (TDDs) as low as 1x106 cm-2 are routinely achieved. Minority carrier lifetime data achieved on GaAs-on-Si layers exploiting this novel SiGe buffer approach to monolithic integration (τp = 10.5 ns and τn = 1.7ns) verifies the high III-V material quality. Single junction GaAs solar cells with high efficiencies for GaAs/Si of 18.1% under AM1.5-G illumination were demonstrated. Further exploiting the novel GaAs/Si material quality, even more complex minority carrier devices including dual-junction solar cells and LEDs were fabricated, yielding high performance consistent with the high III-V/Si mobilities. In both cases, certain device metrics on SiGe outperformed identical GaAs monolithic devices. Finally, a visible laser on Si was achieved, demonstrating the success and further potential of this III-V/Si integration methodology.

Strain modulation of SiGe virtual substrate

We report a technique for modulating the strain of SiGe∕Si virtual substrate by incorporating boron into the Si layer to change its lattice constant. The analysis of Raman measurement shows that the degree of strain relaxation in the SiGe layer increases with the dopant concentration as a result of the lattice contraction in the boron-doped Si layer that produces increased lattice mismatch at the SiGe∕Si interface.

Optical characterization of ZnSe epilayers and ZnCdSe∕ZnSe quantum wells grown on Ge∕Ge0.95Si0.05∕Ge0.9Si0.1∕Si virtual substrates

Several approaches have been employed to grow high-quality ZnSe epilayers on Ge∕Ge0.95Si0.05∕Ge0.9Si0.1∕Si virtual substrates. The ZnSe epilayers were characterized by photoluminescence spectroscopy. Migration enhanced epitaxy and inserting an in situ thermal annealing ZnSe buffer layer effectively reduced the intensity of deep level emissions from the ZnSe epilayer grown on a 6°-tilted Ge∕Ge0.95Si0.05∕Ge0.9Si0.1∕Si virtual substrate. Optimized conditions for growing high-quality ZnSe were used to deposit ZnCdSe∕ZnSe multiple quantum wells on Ge∕Ge0.95Si0.05∕Ge0.9Si0.1∕Si virtual substrates. Photoluminescence spectroscopy revealed quantum-confinement effect in the ZnCdSe multiple quantum wells. The evolution of the exciton emission peak energy and the linewidth as a function of temperature indicate a low density of localized sites in the sample with a well width of 1nm. In the high-temperature regime, the thermal quenching of the excitonic emission intensity from ZnCdSe quantum well structures was governed by the thermal activation of carriers from quantum-well-confined states into barrier states.

Coplanar Integration of Lattice-Mismatched Semiconductors with Silicon by Wafer Bonding Ge / Si1 − xGex / Si Virtual Substrates

We have demonstrated a general process which could be used for the integration of lattice-mismatched semiconductors onto large, Si-sized wafers by wafer bonding virtual substrates. The challenges for implementing this procedure for large diameter Ge-on-insulator (GOI) have been identified and solved, resulting in the transfer of epitaxial to a Si wafer. We found that planarization of Ge virtual substrates was a key limiting factor in the transfer process. To circumvent this problem, an oxide layer was first deposited on the Ge film before planarization using a standard oxide chemical mechanical planarization process. The GOI structure was created using -induced layer exfoliation (Smartcut™) and a buried etch-stop layer, which was used to subsequently remove the surface damage with a hydrogen peroxide selective etch. After selective etching, the crosshatched surface morphology of the original virtual substrate was preserved with roughness of <15 nm rms as measured on a scale and a scale roughness of Using an etch-stop layer, the transferred device layer thickness is defined epitaxially allowing for future fabrication of ultrathin GOI as well as III-V films directly on large-diameter Si wafers. © 2004 The Electrochemical Society. All rights reserved.