Si-SiO2 Interface Traps Research Articles

Effect of Proton Irradiation on Complementary Metal Oxide Semiconductor (CMOS) Single-Photon Avalanche Diodes

The effects of proton irradiation on CMOS Single-Photon Avalanche Diodes (SPADs) are investigated in this article. The I–V characteristics, dark count rate (DCR), and photon detection probability (PDP) of the CMOS SPADs were measured under 30 MeV and 52 MeV proton irradiations. Two types of SPAD, with and without shallow trench isolation (STI), were designed. According to the experimental results, the leakage current, breakdown voltage, and PDP did not change after irradiation at a DDD of 2.82 × 108 MeV/g, but the DCR increased significantly at five different higher voltages. The DCR increased by 506 cps at an excess voltage of 2 V and 10,846 cps at 10 V after 30 MeV proton irradiation. A γ irradiation was conducted with a TID of 10 krad (Si). The DCR after the γ irradiation increased from 256 cps to 336 cps at an excess voltage of 10 V. The comparison of the DCR after proton and γ-ray irradiation with two structures of SPAD indicates that the major increase in the DCR was due to the depletion region defects caused by proton displacement damage rather than the Si-SiO2 interface trap generated by ionization.

Surface Passivation by Quantum Exclusion: On the Quantum Efficiency and Stability of Delta-Doped CCDs and CMOS Image Sensors in Space.

Radiation-induced damage and instabilities in back-illuminated silicon detectors have proved to be challenging in multiple NASA and commercial applications. In this paper, we develop a model of detector quantum efficiency (QE) as a function of Si-SiO2 interface and oxide trap densities to analyze the performance of silicon detectors and explore the requirements for stable, radiation-hardened surface passivation. By analyzing QE data acquired before, during, and after, exposure to damaging UV radiation, we explore the physical and chemical mechanisms underlying UV-induced surface damage, variable surface charge, QE, and stability in ion-implanted and delta-doped detectors. Delta-doped CCD and CMOS image sensors are shown to be uniquely hardened against surface damage caused by ionizing radiation, enabling the stability and photometric accuracy required by NASA for exoplanet science and time domain astronomy.

(Invited) On the Modeling of the Charge Pumping Curves

The Charge Pumping (CP) technique has been used to characterize insulator semiconductor interface traps in numerous device types and in a wealth of situations [1]. A few years ago and for the first time, the three basic CP curves types recorded from conventional silicon MOSFETs with thick SiO2insulating films have been simulated very accurately in a large range of experimental conditions [2, 3], demonstrating that the model derived satisfactorily accounts for the CP mechanisms and that the properties of the traps introduced, i.e. their distribution and electrical characteristics, were plausible. As far as we know no more recent results have been published in that field. Indeed, one may expect the electrical CP response of gate stacks with high-k dielectrics to be even more difficult to tackle [1]. A part of the above results has been used more recently to investigate the meaning of CP curve edges [4]. This study pointed out the role that surface potential plays in interface traps filling and in CP curves shape. It was also shown that the Si-SiO2interface trap density, Dit, usually extracted as proposed in [5], can be very simply obtained from the slope of the CP curve edges [4]. Besides, a few months ago, several Pbo centers, the amphoteric defect well-known to be the main trap type at the Si(100)-SiO2 interface after SiO2 growth have been identified in deep submicron area MOSFETs [6], pursuing the story of the Si-SiO2interface electrical characterization. In this paper, starting from the results presented in [2, 3], the essential of the model, the major advances with regard to previous work and the main conclusion that can be drawn concerning the CP mechanisms will be recalled. The impact of the gate signal parameters on carrier capture and emission will be detailed. The contributions to the overall CP signal of the different traps introduced along with the impact on the CP curve shape of their characteristics will be presented. The limitations of this approach will also be pointed out. [1] Nanoscale CMOS – Innovative Materials, Modeling and Characterization, Ch. 15, Characterization of interface defects, by P. Hurley, O. Engström, D. Bauza, and G. Ghibaudo, Edited by F. Balestra, Ed. ISTE-Wiley 2010. [2] D. Bauza, IEEE Trans. Electron Devices 56, 70, (2009). [3] D. Bauza, IEEE Trans. Electron Devices 56, 78, (2009). [4] D. Bauza, International Reliability Physics Symposium (IRPS) 2013, paper GD-2. [5] G. Groeseneken, H.E. Maes, N. Beltran, and R. F. De Keersmaeker, IEEE Trans. Electron. Devices 31, 42 (1984). [6] T. Tsuchyia and Y. Ono, Jap. J. Appl. Phys. 54, 04DC01 (2015).

Comparison between Equilibrium Voltage Step and Charge Pumping Techniques for Characterizing near Si-SiO2 Interface Traps

In conventional MOS structures, the interface region between silicon and its oxide contains defects which play an important role in the performance and reliability of the devices by acting as charge traps. Traps having response times greater than that of conventional (and so-called “fast”) interface traps are known as slow traps. These traps are supposed to exchange charges with the semiconductor by tunnelling, their response time depending on their energy level and distance from the interface. Due to their wide range of response times and depending on the measurement technique employed, they are often indistinguishable from fast ones or from fixed oxide charges.Several techniques have been used to characterize electrically these different kinds of traps in MOS capacitors or MOSFET structures. Recently, the study on MOS capacitors of current transients that follow the application of a small gate voltage step due to the change in the charge state of the traps has been proposed by Tanner & al. [1]. The technique was used to characterize traps generated in the oxide by constant current stressing [1]. A few years later, Spillane et al. [2] introduced the McWhorter tunnelling model [3] to evaluate oxide depth from the traps time constant and study the slow states density versus oxide depth.In this paper, after recalling the principle of the Equilibrium Voltage Step (EVS) technique, this technique is used to extract the profile in three dimensions (Nt, x, E) of the trap density near the Si-SiO2interface of a lightly stressed MOS structure (Fig. 1). This has been achieved using the models depicted in Refs. [2] and [4] using a device with a rather low interface states density.These results are summarized in two dimensions (Nt,x) in Fig. 2 where they are compared with those obtained with charge pumping (CP) [4], [5]. A good coherence between the results recorded using the two techniques is obtained. The traps densities measured using EVS are in the same order of magnitude as those obtained with CP. Both trap profiles show the same tendencies even though their shapes are somewhat different. From that point of view, CP may be more efficient in distinguishing between interface and near oxide traps. However, the shape of trap profiles extracted previously using current-DLTS [6] is very close to that measured here using EVS method. In this paper, these results will be compared and discussed.[1] P. Tanner, S. Dimitrijev, and H.B. Harrison, Electronics Letters, 31, 1880 (1995).[2] M. P. Spillane, S. Taylor and M. J. Uren, Microelectronic Engineering, 48, 155 (1999).[3] A. L. McWhorter, Semiconductor Surface Physics, Univ. Pennsylvania Press, 1957, pp. 207-228. [4] D. Bauza and Y. Maneglia, IEEE Trans. Electron Devices, 44, 2262 (1997).[5] Y. Maneglia, F. Rahmoune and D. Bauza, J. Appl. Phys., 97, 145021 (2005).[6] D. Bauza, J. Appl. Phys., 84, 6178 (1998).

Comparison between Equilibrium Voltage Step and Charge Pumping Techniques for Characterizing near Si-SiO2 Interface Traps

The Equilibrium Voltage Step (EVS) technique has been used for extraction of depth and energy concentration profile of traps situated in the oxide of a lightly stressed metal-oxide-semiconductor (MOS) structure. This has been achieved up to the very near Si-SiO2 interface. The results are discussed and compared with those obtained using charge pumping (CP) technique. A good agreement is achieved between the trap densities extracted using the two methods even though differences in the shape of the profiles can be observed. The results also very well agree with those published previously using current deep level transient spectroscopy (C-DLTS).

Detailed Analysis of Si-SiO2 Interface Traps in State-of-the-Art MOSFETs Using Charge Pumping

Based on charge pumping (CP) mechanisms, the way Si-SiO2 interface traps interact with the gate CP signal in state-of-the-art MOSFETs with a thick SiO2 gate dielectric is detailed. The consequences that can be deduced or studied from the previous results are presented. This includes the way the interface is probed, the slope of the CP curves and the resulting interface trap density extraction from them. The dependence of CP curves with gate signal frequency and the high frequency limit case are dealt with using simulation. Both are very well accounted for, providing new information on Si-SiO2 interface trap characteristics.

Detailed Analysis of Si-SiO2 Interface Traps in State-of-the-Art MOSFETs Using Charge Pumping

not Available.

(Invited) Charge Pumping and Si-SiO2 Interface Traps Electrical Characterization

After recalling recent results obtained in the field of the electrical characterization of the Si-SiO2 interface traps in conventional MOS transistors and in MOSFET's having HfO2 as gate dielectric using the charge pumping (CP) technique, the paper focuses on the slope of the CP curves.

Charges Pumping and Si-SiO2 Interface Traps Electrical Characterization

not Available.

Analysis of Si–SiO2 Interface Using Charge Pumping Method with Various Capping Materials between Gate Stacks and Inter Layer Dielectric in NAND Flash Memory

We report the dependence of Si–SiO2 interface trap density after Fowler–Nordheim (F/N) stress on various capping materials between gate stacks and an inter layer dielectric (ILD) in a NAND Flash memory cell. The interface trap density was characterized by charge pumping method (CPM). When the capping layer is an oxide, the Nit after F/N stress is approximately 2×1011 cm-2, which is about 50% smaller than that with a nitride layer. We found that the oxide layer causes compressive stress whereas the nitride layer causes a relatively high tensile stress in the underlying substrate by measuring the warp change of the substrate. To correlate the interface state density and data retention characteristics, we measured Vt shift after high-temperature baking. When an oxide capping layer is used, the retention characteristics of memory devices are greatly improved compared to the nitride capping case. These results show a good correlation between the interface characteristics and mechanical stress behaviors.

On the Si–SiO2 interface trap time constant distribution in metal-oxide-semiconductor transistors

The reliability of a charge pumping (CP) technique proposed recently, which allows the extraction of the Si–SiO2 interface trap concentration profiles in metal-oxide-semiconductor transistors, from fast to slow traps, is discussed. The shape of the trap concentration profiles measured, the values of the trap cross section extracted, and the integration of the trap profiles, which should give the interface trap density obtained using the conventional CP technique, are discussed with regard to the trap filling function variation and to surface-potential fluctuations. Then, the influence, on these profiles, of both carrier emission, which is neglected in the model used for calculating the profiles, and of the source and drain regions (S/D-R) of the devices, where the threshold and flatband voltages are different from those in the central region of the channel, is investigated. It is shown that carrier emission does not impact on the trap profiles and that the trap time constant distribution measured does not originate from the S/D-R of the devices. A way to detect a significant contribution of these regions to the charge pumping current measured is proposed. Finally, a comparison with noise spectroscopy is carried out. The results obtained using the two techniques agree very well.

Si-SiO2 interface trap density in boron- and phosphorus-implanted silicon

The Si-SiO2 interface trap density has been measured in boron- and phosphorus-implanted silicon. The implantations were made either prior to the oxidation process or through the gate oxide layer. In the boron implantation case the lowest number of interface traps for a specified substrate concentration was reached if the implantation was made through the gate oxide. In the phosphorus implantation case it is, however, favorable to make the implantation prior to the oxidation process.

Models of Si-SiO2 interface reactions

Si-SiO2 interface traps are typically annealed at a low temperature (300-450 degrees C) in the presence of hydrogen. Despite the widespread acceptance and importance of this technique, the rates and mechanisms of trap annealing are not well understood. Several recent papers have presented kinetic descriptions of Si-SiO2 interface trap annealing. The author investigates the application of these kinetic results to models of Si-SiO2 interface chemical reactions. Directions for further inquiries are described.

Chemistry of Si-SiO2 interface trap annealing

The kinetics and chemistry of Si-SiO2 interface trap annealing are examined in detail. Measurements of interface trap density Dit as a function of anneal time were performed with several process variables as parameters: oxide thickness, anneal ambient, temperature, bulk carrier type, metallization damage, and orientation. Experiments were carried out using rapid thermal processing and capacitance-voltage measurements of aluminum gate metal-oxide-semiconductor capacitors. Anneal temperature and crystal orientation have the strongest effect on the kinetics. 〈100〉 interfaces can be described by a power-law temporal variation; 〈111〉 kinetics are slightly more complicated. In both cases the experimentally observed anneal behavior is in conflict with the commonly used second-order surface recombination model. We propose a two-reaction model involving atomic hydrogen dimerization and hydrogen/interface trap reactions. This model sucessfully predicts anneal kinetics over a temperature range of 170–500 °C, representing a 106 dynamic range in anneal rates. The difference in anneal behavior between 〈111〉 and 〈100〉 interfaces is explained by postulating different trap anneal mechanisms for the Pb0 and Pb1 defect centers. This hypothesis is supported by trap production kinetics induced by extended anneals.