Si Gate Structure Research Articles

Impact of Saturated Spontaneous Polarization on the Endurance Fatigue of Si FeFET With Metal/Ferroelectric/Interlayer/Si Gate Structure

Impact of Saturated Spontaneous Polarization on the Endurance Fatigue of Si FeFET With Metal/Ferroelectric/Interlayer/Si Gate Structure

Fixed charges at the HfO[formula omitted]/SiO2 interface: Impact on the memory window of FeFET

In this article, the impact of interfacial fixed charges on the memory window (MW) of HfO2-based ferroelectric field-effect transistor (FeFET) is investigated using technology computer-aided design (TCAD) device simulations. We have considered the presence of fixed charges at the interface between the ferroelectric layer (FE) and the interlayer dielectric (IL) of FeFET with metal/ferroelectric/interlayer/Si (MFIS) gate structure. Our study indicates that the presence of fixed charges affects the polarization and corresponding depolarization field in the ferroelectric. Positive and negative interface charges can align the polarization direction. The MW degradation is observed with the increase in the fixed charge concentration (Qf).

Experimental Extraction and Simulation of Charge Trapping During Endurance of FeFET With TiN/HfZrO/SiO2/Si (MFIS) Gate Structure

We investigate the charge trapping during endurance fatigue of FeFET with TiN/Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si (MFIS) gate structure. We propose a method of experimentally extracting the number of trapped charges during the memory operation, by measuring the charges in the metal gate and Si substrate. We verify that the amount of trapped charges increases during the endurance fatigue process. This is the first time that the trapped charges are directly experimentally extracted and verified to increase during endurance fatigue. Moreover, we model the interplay between the trapped charges and ferroelectric polarization switching during endurance fatigue. Through the consistency of experimental results and simulated data, we demonstrate that as the memory window (MW) decreases: 1) the ferroelectric characteristic of Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is not degraded; 2) the trap density in the upper bandgap of the gate stacks increases; and 3) the reason for MW decrease is increased trapped electrons after program operation but not related to hole trapping/detrapping. Our work is helpful to study the charge trapping behavior of FeFET and the related endurance fatigue process.

Impact of Charges at Ferroelectric/Interlayer Interface on Depolarization Field of Ferroelectric FET With Metal/Ferroelectric/Interlayer/Si Gate-Stack

This article theoretically investigates the impact of charges at the ferroelectric/interlayer interface on the depolarization field of ferroelectric FET (FeFET) with metal/ferroelectric/interlayer/Si gate structure. The interfacial charges include fixed charges and trapped/detrapped charges. We find that the positive or negative interfacial charges (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ) can align the directions of the depolarization field and corresponding polarization in the ferroelectric. This article may provide insight into the device design of FeFET.

Effect of post-deposition annealing on charge distribution of metal-oxide-semiconductor capacitor with TiN/HfO2/SiO2/Si gate structure

We experimentally investigate the effect of post-deposition annealing on the charge distribution of a metal-oxide-semiconductor capacitor with a TiN/HfO2/SiO2/Si gate structure. We decoupled interfacial charges at the SiO2/Si and HfO2/SiO2 interfaces; bulk charges in HfO2; and the dipole formation at the HfO2/SiO2 interface. The interfacial charges at the HfO2/SiO2 interface decreased and the dipole increased after H2 or N2 annealing. Oxygen dangling bonds are the physical origin of the charges at the HfO2/SiO2 interface. The interfacial charges at the SiO2/Si interface and the bulk charges in HfO2 are almost unchanged.

Bias dependent potential distribution of a Pt/HfO2/SiO2/Si gate structure obtained from a bias application in hard X-ray photoelectron spectroscopy

The electronic states and potential distribution throughout a Pt gate metal/high-k gate-stack structure were investigated using a bias application in hard X-ray photoelectron spectroscopy. Analyzing the core level shifts as functions of the applied bias voltage indicates that a potential gradient forms at the Pt/HfO2 interface.

High Temperature Annealing of the Interface State Component of Negative-Bias Temperature Instability (NBTI) in MOSFET Devices

We have performed negative bias instability (NBTI) measurements on 130 nm channel length Si MOSFETs with SiON gate dielectrics at different temperatures up to 220 °C. Using a pulsed stressiing and pseudo-DC measurements we have focused on the charging and annealing kinetics of only the interface state related component. At temperatures > 180 °C we find clear evidence for a diminution of the growth kinetics suggesting the onset of an annealing effect during interface state generation. We contrast the NBTI data with interface state growth in devices exposed to ionizing radiation. Possible physical mechanisms contributing to the “annealing” effect are discussed and associated with diffusing H2 molecules present in the substrate/gate insulator/polycrystalline Si gate structure.

Formation and properties of ultrathin layers for fabrication of SOI MOS nanotransistor elements

The methods of manufacturing and properties of elements of the SOI MOS nanotransistor such as the gate/gate dielectric, source/drain regions and ohmic contacts have been considered. The HfO2(50 nm)/Si (100) and W/HfO2(4 nm)/Si (100) gate structures have been fabricated using the radio-frequency magnetron sputtering method. It is shown that the crystalline structure of the HfO2 films and their electrical characteristics (breakdown voltage) are interrelated. To produce ultrashallow source/drain regions, a high-dose plasma-immersion boron ion implantation is used. In the process of the rapid thermal annealing of the implanted layers, a substantial reduction in the boron amount near the surface of the SOI structure is detected. The CoSi2 ohmic contacts were made using the Ti(8 nm)/Co(10 nm)/Ti(5 nm) structures formed on a Si substrate of (100) orientation. It is established that the CoSi2 film formed as a result of two-stage annealing possesses a surface resistance of ∼20 Ohm/□.

Fabrication and Characterization of MFIS-FET Using Au/BLT/LZO/Si Structures

We fabricated the n-channel metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) using an Au/(Bi,La) 4 Ti 3 O 12 /LaZrO x /Si(100) gate structure. We observed that the LaZrO x thin film had the equivalent oxide thickness value of around 8.7 nm. The 420-nm-thick (Bi,La) 4 Ti 3 O 12 film on a LaZrO x /Si structure, showed a good ferroelectric property and had the width of the memory window of 1.2 V for a bias voltage sweeping of ± 7 V. The drain current-gate voltage (I D -V G ) of an Au/(Bi,La) 4 Ti 3 O 12/ LaZrO x /Si(100) MFIS-FET showed threshold voltage shift (memory window width) owing to the ferroelectric (Bi,La) 4 Ti 3 O 12 film. The drain current-drain voltage (I D -V D ) characteristic curves exhibit typical n-channel field-effect transistor current-voltage characteristic. However, relatively large leakage current observed in the I D –V G and the I D –V D characteristic curves, might be caused by the high density of pores in the BLT film.

Fabrication and characterization of metal-ferroelectric-insulator-Si diodes and transistors with different HfSiON buffer layer thickness

Metal-ferroelectric-insulator-Si (MFIS) structures using HfSiON as buffer layers were fabricated, and the impact of buffer layer thickness on the electrical properties of the MFIS devices was investigated. HfSiON films with thickness ranging from 1 to 4 nm were deposited by electron beam evaporation, which exhibited much reduced leakage current when compared to that of SiO2 with the same equivalent oxide thickness. From the viewpoint of polarization and charge injection, the flatband voltage and memory window width dependent on the sweeping voltages were discussed for the MFIS diodes with 1-, 2-, and 4-nm-thick HfSiON buffer layers. Small leakage current as well as excellent long-term data retention characteristics were found for all of these samples. It was also found that MFIS diodes with 2-nm-thick HfSiON buffer layer have the largest memory window width. Ferroelectric-gate transistors fabricated with a Pt/SBT(300nm)/HfSiON (2 nm)/Si gate structure showed a memory window of 0.8 V and a high drain current on/off ratio of 108 for the gate voltage sweep between +4 and −4 V. All of these excellent electrical properties proved that HfSiON acts as an excellent barrier for suppressing both leakage current and atomic interdiffusion.

Characterization of HfTaO films for gate oxide and metal-ferroelectric-insulator-silicon device applications

Characteristics of HfTaO thin films have been investigated from the viewpoints of their applications as insulating buffer layer in the metal-ferroelectric-insulator-semiconductor (MFIS) structure and gate oxide for next generation metal-oxide-silicon devices. HfTaO films with 2, 4, and 6nm in thickness have been deposited on Si substrates using electron beam evaporation and annealed typically at 800°C for 1min in O2 atmosphere. In fabrication of MFIS diodes, SrBi2Ta2O9 (SBT) films have been deposited on HfTaO using a sol-gel spin-coating method. It has been found from C-V (capacitance versus voltage) and I-V (current versus voltage) characteristics of Al∕HfTaO∕Si diodes with different film thicknesses that the optimum annealing temperature is 800°C and the dielectric constant of HfTaO is about 17. For MFIS devices with Pt∕SrBi2Ta2O9 (300nm)∕HfTaO(4nm)∕Si gate structures, a memory window of 0.65V between +4 and −4V gate voltage sweeping was observed. Furthermore, the high and low capacitance values biased at the center of the hysteresis loop are clearly distinguishable for over 24h, demonstrating excellent long-term retentions properties.

Recent Progress in Ferroelectric Random Access Memory Technology

AbstractIn this paper, ferroelectric materials suitable for realizing high-density 1T1C-type (capacitor-type) FeRAM are first reviewed. It is found in BiFeO3(BFO) films formed by chemical solution deposition that leakage current density at a low electric field increases by substitution of Mn and Cr atoms for Fe atoms. But, it is also found that the breakdown characteristic is much improved by substitution of these atoms. Because of the better breakdown characteristic, the leakage current densities in the 3 and 5% Mn-substituted films are lower than that in an undoped BFO film at an applied electric field of 1MV/cm at room temperature, and thus well saturated hysteresis loops in P-E (polarization vs. electric field) characteristics are observed in these films.Next, recent technological progress in transistor-type FeRAM, in which data are stored in a single ferroelectric-gate FET(field effect transistor), is discussed. It is demonstrated that the data retention time of ferroelectric-gate FETs is much improved by use of HfO2-based buffer layers which are inserted between the ferroelectric film and Si substrate for preventing interdiffusion of constituent elements. Particular attention is paid to FETs with a Pt/SrBi2Ta2O9/HfO2/Si gate structure, in which the data retention time longer than 30 days has been attained. Finally, the cell structure and operation principle of 1T (one transistor)-type FeRAM are discussed.

APPLICATIONS OF BISMUTH-LAYERED PEROVSKITE THIN FILMS TO FET-TYPE FERROELECTRIC MEMORIES

ABSTRACT Recent progress in FET (field-effect transistor)-type ferroelectric random access memories is reviewed. Effectiveness of a HfO2 buffer layer, which is inserted between a ferroelectric film and Si substrate for preventing interdiffusion of constituent elements, is first described. It is shown in the FET with Pt/SrBi2Ta2O9/HfO2/Si gate structure that the drain current on/off ratio is larger than 103 even after 30 days have elapsed. Then, the operation principle of a 1T2C-type memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of a MOSFET, is discussed and basic characteristics of a 1 kbit array composed of 1T2C-type cells are presented.

Memory operation of Pt–SrBi 2Ta 2O 9–Y 2O 3–Si field-effect transistor with damage-free selective dry etching process

Metal–ferroelectric–insulator–semiconductor field-effect transistor (MFISFET) with Pt–SrBi 2Ta 2O 9 (SBT)–Y 2O 3–Si gate structure was fabricated with a selective dry etching of SBT and Y 2O 3. The etching characteristics of SBT, Y 2O 3, and silicon were investigated with various Ar/Cl 2 gas mixing ratios. Inductively coupled plasma (ICP) Powers, and RF bias powers and the surface condition after the etching was analyzed by using the scanning electron microscopy (SEM), atomic force microscopy (AFM), X-ray photoemission spectroscopy (XPS), and Rutherford back scattering (RBS) measurement. The etch-stop process was successfully achieved at the condition of 50% Cl 2 concentration with the ICP power of 900 W and the RF bias power of 100 W where the selectivity of SBT to Y 2O 3 was 4. The fabricated MFISFET with the etch-stop process showed good memory operation with 1.2 V threshold voltage difference and more than three orders of drain current difference in the on/off drain current ratio at the operating voltage of 7 V. These results meant that the etch-stop process was successfully carried out and applied to MFISFET fabrication without degradation of the ferroelectric characteristics and damage on silicon surface.

Impact of HfO2 buffer layers on data retention characteristics of ferroelectric-gate field-effect transistors

Electrical properties of the p-channel metal-ferroelectric-insulator-silicon field-effect transistors (MFISFETs) using Pt∕SrBi2Ta2O9(SBT)∕HfO2∕Si and Pt∕(Bi,La)4Ti3O12(BLT)∕HfO2∕Si gate structures were investigated. Sol-gel-derived 400-nm-thick SBT and BLT films were deposited on an HfO2 film of approximately 10 nm in thickness. The channel width and channel length of the fabricated MFISFETs were 50 and 5 μm, respectively. The significant drain current on∕off ratios were retained for over 10 days at room temperature. The fabricated MFISFETs using a Pt∕SBT∕HfO2∕Si gate structure exhibited a drain current on∕off ratio of about 105 even after 15.9 days had elapsed. It was also found in the fabricated MFISFETs that a write pulse width as short as 20 ns was enough for obtaining the significant drain current on∕off ratio. It is concluded from these results that HfO2 is one of the best buffer layer materials for realizing MFISFETs with long data retention and high operation speed.

Fabrication of MFISFETs with Pt/SrBi2Ta2O9/Y2O3/Si gate structure by developing an etch-stop process

A metal–ferroelectric–insulator–semiconductor field-effect transistor (MFISFET) was fabricated with an etch-stop process based on the selectivity between SrBi2Ta2O9 (SBT) and Y2O3. Depending on the selectivity with various Ar/Cl2 gas mixture, we could find the acceptable thickness of Y2O3 for a successful etch-stop process. The electrical characteristics of the MFISFET fabricated with the developed etch-stop process showed no damage of the silicon surface of source/drain regions, resulting in good ferroelectric memory characteristics and programmable operation. (© 2004 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Multiple Bit Operation of MFISFET With Pt/SrBi2Ta2O9/Y2O3/Si Gate Structure

A single transistor type ferroelectric memory with multiple bit operation was presented. This cell has a metal ferroelectric insulator semiconductor field effect transistor structure. Y2O3 thin film was used as a buffer insulating layer to improve the memory characteristics and SrBi2Ta2O9 was used as a ferroelectric gate material. The multi-level characteristics of four levels with one order of drain current difference were measured according to the writing voltage step of two volt. This multi-level memory cell enables to increase the density of memory in the same space and lower the cost.

Long Time Data Retention and A Mechanism in Ferroelectric-Gate Field Effect Transistors with HfO2 Buffer Layer

ABSTRACTA mechanism of the long-time data retention in the p-channel MFIS FETs with Pt/SBT/HfO2/Si gate structures was proposed. The MFIS FETs used in this study exhibited the drain current on/off ratio of approximately 6×103 even after 30 days had elapsed at room temperature. From the leakage current characteristics of the MFIS diode, the bulk leakage current density lower than 10-12 A/cm2 was presumed for 30-days data retention. On the other hand, we showed that the decrease of on-state drain current in the retention characteristics was explained by the flat-band voltage shift of approximately -0.3V for 30 days toward negative voltage direction. Therefore, it was also found that the trapped charge density as low as 1011 cm-2 was needed for obtaining the data retention of 30 days.

Oxygen plasma rapid thermal annealing to improve the electrical properties of Pt–SrBi[sub 2]Nb[sub 2]O[sub 9]–SiO[sub 2]–Si gate structure

A rapid thermal annealing (RTA) method in oxygen plasma improves the ferroelectric properties of SrBi2Nb2O9 (SBN) film at relatively lower temperature than the conventional furnace annealing in oxygen ambient. The oxygen plasma RTA raises the oxygen content from 44 to 48 at. %, which may improve the oxygen deficiency in the SBN films. The thickness of SiO2 becomes thinner due to the shorter RTA time. As a result, a typical effective memory window of the Pt–SBN–SiO2–Si gate structure is increased from 0.17 to 0.49 V at 3 V of the applied gate bias and the remnant polarization is also increased from 18.03 to 22.6 C/cm2 at ±6 V. The flat band voltage shift of the oxygen plasma RTA samples is quite stable and smaller than that of the furnace annealed ones because charge trapping is relatively smaller at the interface between Si and the oxygen plasma annealed SBN film.

Improvement of ferroelectric properties of Pt–SrBi2Nb2O9–SiO2–Si gate structure through oxygen plasma rapid thermal annealing

A rapid thermal annealing (RTA) method in oxygen plasma improves the ferroelectric properties of SrBi2Nb2O9 (SBN) film at relatively lower temperature compared with the conventional furnace annealing in an oxygen ambient. The oxygen plasma RTA is assumed to improve the oxygen deficiency in the SBN films by increasing the oxygen content from 44 to 48 at%. The thickness of SiO2 becomes less in substantially less time, thereby improving the memory window of the Pt–SBN–SiO2–Si gate structure. The typical effective memory window is increased from 0.17 to 0.49 V at 3 V of the applied gate bias and the double remnant polarization (2Pr) is also increased from 18.03 to 22.6 μC/cm2. The flat-band voltage shift in the case of oxygen plasma RTA is quite stable and smaller than that in the case of furnace annealing because charge trapping is relatively less at the interface between Si and the oxygen plasma RTA-annealed SBN film. (© 2004 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)