Si Cap Thickness Research Articles

A Near-Infrared pin Photodetector of Strain-Enhanced Ge Layer Epitaxially Grown on a Bonded Si-on-Quartz Wafer

In Si photonics, photodetectors (PDs) of a Ge epitaxial layer on Si have been widely used, which show a high photodetection efficiency, or a high responsivity in the O (1.260–1.360 µm) and C (1.530–1.565 µm) bands. However, an issue lies in a low responsivity in the longer wavelength range of L band (1.565–1.625 µm). In this regard, we have proposed a method using a Ge layer epitaxially grown on a Si-on-quartz (SOQ) wafer [1]. The tensile in-plane lattice strain, derived from the thermal expansion mismatch between the Ge layer and base substrate, is enhanced more than 0.3% in Ge on SOQ, despite ~0.2% on Si (or Si-on-insulator). The enhanced strain in Ge on SOQ extends the fundamental optical absorption edge to about 1.65 µm, leading to a potential increase in the L-band responsivity. In this study, a vertical pin PD is fabricated using a Ge layer on SOQ, showing an increased responsivity in the L band.A bonded SQQ wafer was used as the starting substrate, fabricated by Shin-Etsu Chemical Co. Ltd. The top Si (001) layer was 200 nm in thickness, and was heavily doped p-type by B implantation. An undoped Ge epitaxial layer (500 nm) was grown by chemical vapor deposition using GeH4 as the source gas, followed by a growth of Si cap layer (50 nm) using Si2H6. In the top region of Ge layer as well as in the Si cap layer, a heavily n-type doping was carried out by P implantation, forming a vertical pin junction. Finally, a Ti/TiN electrode was formed. Responsivity spectra were measured in the wavelength range of 1.46–1.64 µm at a normal incidence. A reference pin PD was also fabricated using a Ge layer on a standard bulk Si wafer. According to x-ray diffraction measurements, the Ge layer on SOQ showed a tensile strain of 0.33%, despite 0.14% for the reference Ge on Si.Figure 1(a) shows typical current–voltage curves for a pin diode of Ge on SOQ measured under dark and under an illumination of 1.55-µm light (1.1 mW). The diode showed a good rectifying property under dark, while under the illumination, the current in the reverse bias significantly increased, showing a reasonable PD operation. Figure 1(b) shows typical responsivity spectra at a reverse bias of 1 V for PDs of Ge on SOQ and reference Ge on Si. Circles and lines correspond to experimental data points and theoretical curves, respectively. The responsivity for Ge on SOQ was larger in the measured wavelength range of 1.46–1.64 µm, including the L band. The increased responsivity is ascribed to the enhanced tensile strain. However, the increase in the L band was found to be suppressed by a high reflectance because of the multiple reflections at the interfaces. An optimized Si cap thickness as well as an anti-reflection coating with SiO2 can increase the normal-incidence responsivity as high as 0.3 (0.1) A/W up to 1.60 (1.64) µm without an increase in the Ge thickness.[1] Noguchi et al., J. Appl. Phys. 128, 133107 (2020). Figure 1

Process Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer

In this work we study the epitaxial Si growth with Si2H6 for Ge surface passivation in CMOS devices. The Si-caps are grown on Ge in the hydrogen desorption limited regime at a nominal temperature of 400 °C. We evaluate the process window for the interface state density and show that there is an optimal Si-cap thickness between 8 and 9 monolayers for Dit < 5·1011 cm−2 eV−1. Moreover, we discuss the strong impact of the Si-cap growth time and temperature on the interface state density, which arises from the Si thickness dependence on these growth parameters. Furthermore, we successfully transfer a TmSiO/Tm2O3/HfO2 gate stack process from Si to Ge devices with optimized Si-cap, yielding interface state density of 3·1011 eV−1 cm−2 and a significant improvement in oxide trap density compared to GeOx passivation.

(G03 Best Paper Award Winner) Si-Passivated Ge Gate Sacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate

Germanium is considered as a high mobility channel material for its potential to be introduced in future CMOS technology nodes. Ge surface passivation with a thin silicon layer (Si-cap) has been shown to be efficient for pFETs because of a sufficient valence band offset between Ge and Si-cap, which confines the holes in the Ge layer. Strained Ge pFinFETs outperforming Si pFinFETs due to four times higher mobility have been demonstrated using Si-cap process [1]. Interfacial defects can be further passivated with a high-pressure anneal in H2 resulting in reduced sub-threshold swing and increased mobility in Ge nanowires [2]. Moreover, by using a Si-cap, Negative-bias temperature instability reliability is improved compared to GeOx passivation because of the energy decoupling between holes and defects in SiO2/HfO2 gate stack [3]. However, a Si-cap process poses gate stack scalability issues because in order to achieve sufficient surface passivation, the Si-cap thickness cannot be scaled. An introduction of a high-k interfacial layer instead of a chemical oxide SiO2 could potentially help to scale down equivalent oxide thickness. Integrating thulium silicate (TmSiO) as a replacement of the SiO2 interfacial layer has been demonstrated on silicon, and a hole and electron mobility enhancement compared to SiO2/HfO2 gate stacks has been achieved for an equivalent oxide thickness (EOT) < 1 nm [4]. Moreover, we have previously displayed the compatibility of Tm2O3 with Ge by demonstrating GeOx/Tm2O3 gate stacks with interface state density Dit < 5·1011 eV-1cm-2 [5]. In this work, we integrate TmSiO with a Si-cap process to achieve Dit comparable to GeO2 passivation.In order to evaluate Ge/Si/TmSiO interfaces, MOS capacitors (MOSCAPs) were fabricated on n-type Ge strain relaxed buffers epitaxially grown on n-type Si wafers in a two-step process using GeH4 precursor [6]. Si-caps of different thicknesses were grown at 400 °C using Si2H6. Si growth was confirmed by ellipsometry spectroscopy and testing that the surface is hydrophobic. While trying to keep the Si-cap exposure to air to a minimum, 400 nm PECVD SiO2 was deposited and active areas were defined. After removing the remaining SiO2 from the active areas with 1 % HF, Tm2O3 was deposited by atomic layer deposition (ALD) at 225 °C. Rapid thermal anneal at 550 °C for 60 s in N2 was then employed to form TmSiO layer. High-k HfO2 was deposited by ALD at 350 °C followed by a post deposition anneal in O3 for 10 min. TiN gate metal was deposited at 425 °C by ALD and 500 nm Al was deposited by sputtering for probing purposes. After patterning, the samples were subjected to a forming gas anneal of 10% H2 in N2 at 400 °C for 30 min. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gate stacks were also fabricated as described in [5] with addition of ALD HfO2.Interface state density in the midgap of Ge/Si/TmSiO/Tm2O3/HfO2 gate stacks was evaluated by CV measurements where measured CV characteristics where compared to calculated ones assuming a parabolic Dit distribution. Dit highly depends on Si-cap thickness, as displayed in Fig. 1. An optimal Si-cap thickness corresponding to 40-50 min deposition time provides Dit at midgap ~5·1011 cm-2eV-1 at CET of 4 nm. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gates exhibit similar Dit of 4-5·1011 cm-2eV-1. Interface state density distribution within the band gap of Ge/Si/TmSiO interface with 40 min Si-cap deposition time was evaluated using the conductance method at different temperatures and is displayed in Fig. 2. Dit in the midgap is in agreement with the results obtained from CV measurements, and increases towards the valence and conduction band edges. The oxide trapped charge Qox of 2.5·1010 cm-2 (40 times lower than in the Ge reference devices without Si-cap) was determined from CV measurements and corresponds to only 5 mV hysteresis showing the potential of superior reliability.A Si-cap process with high-k TmSiO interface has been demonstrated on Ge MOS devices. A low Dit comparable to GeOx passivation has been shown. In addition, devices with TmSiO potentially have a superior reliability vs GeOx devices due to low oxide trapped charge density.

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

Three-dimensional System-On-Chip (3D-SoC) technology schemes require wafer-to-wafer bonding combined with good control of the Si thickness and the Si within wafer uniformity [1,2]. As a result, there is a renewed interest in epitaxial strained Si1-xGex as etch stop layer [3]. Epitaxial growth by means of Chemical Vapor Deposition (CVD) offers excellent control of layer thickness and material composition. If needed, the Si cap layer can be in-situ doped. The challenge is to develop low cost epitaxial growth processes without compromising the material quality. Indeed, relaxation of the Si1-xGex layer must be avoided as the presence of threading dislocations in the Si-cap has a detrimental effect on electrical properties and the yield of the devices fabricated afterwards. On the other hand, the Ge concentration in the Si1-xGex layer should be sufficiently high to guarantee etch selectivity with respect to the underlying Si substrate [4]. The Si1-xGex layer also needs to be relatively thick as some material loss cannot be avoided. Etching of the Si-cap layer during wafer back-side thinning must be prevented.In this contribution, we discuss the different challenges for the epitaxial growth of such Si-cap / Si1-xGex // Si-substrate layer stacks, with Si-cap layer thicknesses ranging from 20 to 500 nm and a targeted Ge content in the Si1-xGex layer of 25%. All epi-layers discussed in this work were grown in an ASM Intrepid RP-CVD cluster tool, aiming the highest possible process throughput. To control the epitaxial material quality, fast and reliable in-line metrology and inspection techniques are required. For instance, Wostyn et al. recently reported on inline light scattering measurements, commonly used to determine wafer quality and cleanliness, and have shown that the technique is also suitable to study the crystalline quality after hetero epitaxy [5].Standard deviations in thickness below 1.5% as measured for both the Si0.74Ge0.26 and the Si-cap layers by means of Spectroscopic Ellipsometry illustrate the within wafer uniformity of the epitaxially grown layer stacks. The Si0.74Ge0.26 material quality is confirmed by the presence of well-defined Kiessig fringes on the (004) XRD spectrum. The lack of a surface crosshatch pattern in AFM and the very low haze values as obtained from light scattering measurements using the KLA Surfscan® SP3 indicate the absence of misfit dislocations in uncapped Si0.74Ge0.26 layers for thicknesses up to 100 nm. After Si capping, RSM measurements still indicate that the layer is fully strained (Fig. 1a). Moreover, no defects were detected by commercial in-line defect inspection systems such as the KLA Electron-Beam Wafer Defect Review (EDRT M) System and the automated optical inspection system. However, depending on the process conditions, enhanced haze values might be measured. This enhanced surface roughness is due to the presence of misfit dislocations as evidenced by AFM (Fig. 1b). A careful process optimization enables the deposition of Si-cap / Si0.75Ge0.25 // Si-substrate bilayers with low haze values which are completely free of misfit dislocations, still allowing a Si-cap thickness of up to 500 nm and a relative high processing throughput (Fig. 1d). Still, it is striking that in case of 300 mm substrates, layer relaxation, if present, starts at the edge of the wafer (Fig. 1c) [6]. Therefore, special care needs to be taken to ensure that no relaxation is initiated at wafer edges. Extremely sensitive characterization methods are mandatory to detect the onset of relaxation and to ensure the fabrication of defect-free epi stacks. The developed epi process was successfully implemented in 3D device integration schemes to fabricate stacked Gate All Around devices and to demonstrate functional backside integration.

Advanced Spectroscopic Ellipsometry Application for Multi-Layers SiGe at 28nm Node and Beyond

Spectroscopic Ellipsometry (SE) is a commonly used non-destructive method to perform in-line monitoring of film thicknesses and optical indexes for the semiconductor industry. SE metrology can also monitor film composition by correlating optical indexes to species concentration. Germanium concentration (Ge%) measurement after SiGe epitaxial layer is a critical application at 40/28nm nodes to evaluate strain induced in the PMOS channel;. however, for 28nm and beyond, metrology needs to monitor Ge% on more complex SiGe film processes. This paper describes accurate and stable Ge% measurement on multi-SiGe layers by using optimized optical models and multiple correlation methodologies using SE metrology and how SiGe and Si-cap thicknesses can be reported simultaneously and independently. This paper demonstrates how to create enhanced SiGe models using KLA-Tencor Off-Line Spectral Analysis software based on DoE wafers with wide range split. Five different Ge% conditions are considered and multiple correlations created to report Ge% with less than 1% absolute offset to XRD reference tool. The final measured result also shows excellent Ge% stability (STDEV ~ 0.13%) even when multi-SiGe thicknesses are changed.

High Hole-Mobility Strained-$\hbox{Ge/Si}_{0.6} \hbox{Ge}_{0.4}$ P-MOSFETs With High-K/Metal Gate: Role of Strained-Si Cap Thickness

Low-field effective hole mobility of highly strained (~2.4%, biaxial) germanium-channel (7.8 nm-thick) p-MOSFETs with high-K/metal gate stack has been experimentally investigated. Devices with various ultrathin strained-Si cap layer thicknesses, as thin as ~8 Å, show excellent capacitance-voltage characteristics with no hysteresis or frequency dispersion and hole mobility enhancement of more than 6.5X over Si universal and 2.3X over similar devices with no strained-Si cap, at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> = 0.6 MV/cm. The influence of the strained-Si cap thickness on the hole mobility is also studied. The mobility increases with increasing Si cap thickness up to ~1.8 nm (with a peak mobility of 940 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs at this cap thickness) consistent with a reduction in remote Coulombic scattering.

Effects of Si-cap thickness and temperature on device performance of Si/Ge1−xCx/Si p-MOSFETs

This work presents the effects of Si-cap thickness and temperature on device performance of buried channel Si/Ge1−xCx/Si p-MOSFETs. The silicon-cap thickness (3–9 nm), as well as the operating temperature (300 K down to 77 K), plays a significant role on device performance in terms of drive current, sub-threshold slope, effective hole mobility and Ion–Ioff ratio. The 7 nm Si-capped device demonstrates highest mobility enhancement because of reduced remote Coulomb scattering. In addition, the valence band offset between the Si-cap/Ge1−xCx interface was quantitatively extracted by fitting the stair-case behavior of split C–V characteristics with self-consistent simulations of one-dimensional Poisson and Schrodinger equations.

Optimizing the growth of CoSi 2 film with oxide-mediated CoSi 2 template by silicon cap layer

Applying both template and Si cap technology, we achieved the epitaxial growth of CoSi 2 directly on Si(1 0 0) substrate by rapid thermal annealing (RTA). The crystal quality of CoSi 2 film is found to be significantly dependent on the Si cap thickness. In our work, a good-quality CoSi 2 film with a minimum of χ min~11.6% and 3.3 Ω/square was obtained as a 15 nm Co with a subsequent 15 nm Si cap layer is deposited on an oxide-mediated CoSi 2 template and followed by an anneal at 1050 °C under N 2 protection; whereas too thin or thick Si cap layer will deteriorate the crystalline quality of CoSi 2. These experimental results are discussed in combination with the simulation of Rutherford backscattering spectroscopy and X-ray reflectivity.

An investigation on the light-emission mechanism of metal-insulator-semiconductor light-emitting diodes with different SiGe quantum well structures

The SiGe quantum well (QW) tunneling diodes with different Si cap thickness are designed in this work to investigate the detailed mechanism of light emission for the metal-insulator-semiconductor (MIS) light-emitting diode (LED). At the accumulation (negative) gate bias, the electrons tunnel from the metal gate to the SiGe QW semiconductor substrate (p-type). Meanwhile, the negative gate bias also attracts holes in the interface of insulator and SiGe QW semiconductor and then the tunneling electrons can recombine with holes to emit the infrared. LEDs with different Si/SiGe/Si structure are used to investigate the light-emission mechanism and prove that the region of infrared emission is mainly from the interface of the insulator and semiconductor, not from the neutral region in the semiconductor substrate. The accurate energy band and carrier concentration in the SiGe QW structure with operated bias are also simulated and compared it with the experimental data. It shows that the concentrations of the tunneling electrons, which will be drifted by the gate bias, plays the main role on the light emission and limits the light-emission region near the interface of insulator and semiconductor. This work helps us understand clearly the light-emission mechanism of the MIS LED, developed continuously by our group in the decade.

SiGe nanorings by ultrahigh vacuum chemical vapor deposition

Formation of SiGe nanorings from Si capped Si0.1Ge0.9 quantum dots (QDs) grown at 500 °C by ultrahigh vacuum chemical vapor deposition was investigated. SiGe nanorings have average diameter, width, and depth of 185, 30, and 9 nm, respectively. Based on both Raman and x-ray diffraction results, the formation of SiGe nanorings can be attributed to Ge outdiffusion from central SiGe QDs during in situ annealing. Moreover, the depth of SiGe nanorings can be controlled by Si cap thickness. The Si cap is essential for nanorings formation.

In-Line Characterization of Heterojunction Bipolar Transistor Base Layers by High-Resolution X-Ray Diffraction

The suitability of high-resolution X-ray diffraction (HRXRD) as an in-line measurement tool for the characterization of heterojunction bipolar transistor SiGe base layers and Si cap layers was investigated. We showed that despite of polycrystalline Si on the mask material of patterned wafers, HRXRD measurements performed on an array of small windows yield results which are comparable to those that were obtained on a window which is larger than the size of the source beam, regarding the thickness and the Ge content of the SiGe layers. The possibility to extract layer parameters for active device windows of different sizes was therefore demonstrated. The suitability of HRXRD for in-line measurement of the Si cap thickness was also assessed and the sensitivity of this technique for determining the substitutional boron concentration in SiGe was studied. The detection limit in the monitoring of the active dopant concentration was about 2.7 x 10^19 cm-3.

Growth of oxide-mediated ternary silicide controlled by a Si cap layer by rapid thermal annealing

We reported a simple method to grow good-quality CoSi 2 film by using Si cap technology and introducing moderate Ni. First, a cobalt layer of ∼15 nm with a Si cap layer with a different thickness deposited onto the Si surface with a thin silicon oxide buffer is applied to investigate the formation of CoSi 2 by ex situ rapid thermal annealing. It was found that a 13 nm thick Si cap layer could significantly improve the crystal quality of oxide-mediated CoSi 2 film. Setting the Si cap thickness at 13 nm, we revealed that introduction of Ni can further improve the crystal quality of the silicide film in comparison to the pure Co silicide, and a ratio of Ni to Co at round 1:8 causes the lowest sheet resistance, ∼5 Ω/sq.

Low-Frequency Noise Characteristics in Strained-Si nMOSFETs

The low-frequency (LF) (1/f) noise mechanism of strained-Si nMOSFETs grown on relaxed Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> virtual substrates (VSs) has been investigated. It is found that the Si-cap thickness plays an important role in characterizing the 1/f noise mechanism. Ge out-diffusion effect and slight strain relaxation in Si-cap layer are responsible for the degradation of 1/f noise in strained-Si device with 10- and 20-nm-thick Si-cap, respectively. In addition, by choosing proper Si-cap thickness, experimental result shows that as Si-cap undergoes stronger tensile strain for higher Ge concentration VS, the correlated mobility fluctuation term in the modified carrier-number fluctuation model is more dominated for the 1/f noise

Selective epitaxial Si/SiGe growth for VT shift adjustment in high k pMOS devices

Downscaling of classical metal oxide semiconductor (MOS) devices resulted in a need to replace the gate oxide by high k dielectrics to keep the gate leakage under control. However, new device issues such as an uncontrollable shift in the threshold voltage in p-type MOS devices and a reduction in channel mobility were encountered. These issues can be overcome by the implementation of buried strained SiGe channels, grown by selective epitaxial growth, as demonstrated in this paper. The optimized high k gate fabrication scheme starts with the growth of a very thin oxide layer. Therefore, a Si cap layer is required because oxidation of SiGe leads to defects at the gate/channel interface. The Si growth rate is influenced by the underlying SiGe layer, during the deposition of the first atomic layers. Nevertheless, accurate thickness control of the Si cap is possible. The minimal required Si cap thickness and its dependence on Ge content in the underlying SiGe channel, for making high-quality dielectrics and maintaining low capacitive equivalent thickness, is extracted from charge pumping measurements, CV measurements and energy dispersive x-ray spectroscopy measurements. Device results demonstrate the successful implementation of buried SiGe channels in pMOS devices with high k gate dielectrics.

High performance germanium MOSFETs

Ge is a very promising material as future channel materials for nanoscale MOSFETs due to its high mobility and thus a higher source injection velocity, which translates into higher drive current and smaller gate delay. However, for Ge to become main-stream, surface passivation and heterogeneous integration of crystalline Ge layers on Si must be achieved. We have demonstrated growth of fully relaxed smooth single crystal Ge layers on Si using a novel multi-step growth and hydrogen anneal process without any graded buffer SiGe layer. Surface passivation of Ge has been achieved with its native oxynitride (GeO x N y ) and high-permittivity (high-k) metal oxides of Al, Zr and Hf. High mobility MOSFETs have been demonstrated in bulk Ge with high-k gate dielectrics and metal gates. However, due to their smaller bandgap and higher dielectric constant, most high mobility materials suffer from large band-to-band tunneling (BTBT) leakage currents and worse short channel effects. We present novel, Si and Ge based heterostructure MOSFETs, which can significantly reduce the BTBT leakage currents while retaining high channel mobility, making them suitable for scaling into the sub-15 nm regime. Through full band Monte-Carlo, Poisson-Schrodinger and detailed BTBT simulations we show a dramatic reduction in BTBT and excellent electrostatic control of the channel, while maintaining very high drive currents in these highly scaled heterostructure DGFETs. Heterostructure MOSFETs with varying strained-Ge or SiGe thickness, Si cap thickness and Ge percentage were fabricated on bulk Si and SOI substrates. The ultra-thin (∼2 nm) strained-Ge channel heterostructure MOSFETs exhibited >4× mobility enhancements over bulk Si devices and >10× BTBT reduction over surface channel strained SiGe devices.

Promoting emitter diffusion process and optimization of vertical profiles for high-speed SiGe HBT/BiCMOS

A high-temperature anneal-resistant process, which enables high-speed SiGe HBTs to embed scaled CMOS, is optimized in SiGe BiCMOS technology. This process, called promoting emitter diffusion (PED), is based on enhanced phosphorous diffusion from poly-Si emitter electrodes at high temperature to fabricate thin base layers and shorten the base transit time. By investigating the dependence of high-frequency performance on diffusion temperature, as-grown base layer thickness, and Si cap thickness, the methodology for PED optimization was yielded. In addition, this PED process is effective in reducing an extrinsic base resistance due to deep boron diffusion from poly-Si base electrodes. This indicates that the PED process is very effective at improving the tradeoff relationship between cutoff frequency f/sub T/ and maximum oscillation frequency f/sub max/ in self-aligned SiGe HBTs using selective epitaxial growth. As a consequence, both f/sub T/ and f/sub max/ of more than 200GHz were successfully obtained.

Thermal stability study of Si cap/ultrathin Ge/Si and strained Si/Si1−xGex/Si nMOSFETs with HfO2 gate dielectric

The thermal stabilities of MOSFETs with high-K gate dielectric on both Si/ultrathin Ge/Si (SGS) and strained Si on relaxed Si1−xGex (SS) substrates are studied. Though an initial drivability enhancement of 29% is shown for the SGS nMOSFET, annealing at 750 °C has resulted in drastic degradation in its drivability, lowering its Id beyond that of the Si nMOSFETs by 52%. Despite lowering in the junction leakage current, Ge diffusion to the near surface region, indicated by Vth and surface roughness change, degrades the SGS device performance significantly. For the SS nMOSFET, drivability varies with Ge content, whereby a maximum of 86% improvement over that of the Si nMOSFET is observed for 30% Ge. In contrast to the SGS nMOSFET, the SS nMOSFET is able to retain its Id improvement, even after annealing at 950 °C, as the in-plane tensile strain is preserved. Ge diffusion to the surface does not affect the device significantly, as the strained Si thickness is about 10 nm compared to a Si cap thickness of only 1.5 nm for the SGS substrate.

SON (Silicon On Nothing) PLATFORM FOR ULSI ERA: TECHNOLOGY&DEVICES

In this article is presented the new SON process, which key point lies in the transfer of the lattice continuity from a bulk Silicon substrate via a SiGe layer to the Silicon cap layer, both of these layers being obtained by epitaxy. The thin SiGe layer is next removed from underneath the Si cap in an isotropic plasma-assisted chemical dry-etching. The mono-crystalline Si cap layer resulting from this process lies on an air-gap, which gives the name (Silicon On Nothing) to the process. Depending on application, this air-gap may be refilled with a dielectric or with a gate material for double gate applications. In both cases, the thickness of the Si cap as well as that of the air-gap (filled by the dielectric for single gate applications) may be in the range of a few nanometers with a control in the range of the epitaxy process capability. In this article we present the SON process and its implementation to MOSFETs devices and circuits. This development effort converges towards an SON technological platform, allowing easy co-integration of SON and bulk transistors, Gate All Around or multi-gate devices.

Design of Intrinsic and Extrinsic Base Process of HBT using Blanket SiGeC Epitaxial Growth

The profile design methodology of a blanket SiGeC epitaxial layer for hetero junction bipolar transistor (HBT) is presented. Two important factors, Ge profile and Si cap are designed to minimize the carrier transit time in the intrinsic base region. Concurrently, a BF2 ion implantation and a cobalt silicide process for the extrinsic base were optimized to accommodate the Si cap thickness without relaxing a strain in SiGe layers caused by a reaction between Ge and Co. This design resulted in HBTs with 94-GHz cut-off frequency (fT), 81-GHz maximum oscillation frequency (fmax), and 0.45 dB minimum noise figure at 2 GHz, which could be utilized for consumer electronics products operating within a 2-5 GHz frequency range. The HBT was successfully implemented into 0.25-μm CMOS process with various kinds of passive devices to produce LSIs for consumer wireless electronics.

Halo implant in pseudomorphic SiGe channel p-MOSFET devices to reduce short channel effect

Halo ion implantation was adopted to reduce the short channel effect (SCE) of a buried channel p-MOSFET device on pseudomorphic Si0.70Ge0.30 layers. The strained pseudomorphic Si0.70Ge0.30 layer of 10 nm thickness, with a Si cap layer on top, was grown using molecular beam epitaxy. The results show an overall reduction in threshold voltage (Vth) roll-off in both Si and pseudomorphic SiGe devices. Halo implantation of As+, 120 keV and dose 2 × 1013 cm−2, was successfully used to reduce roll-off for the 2 nm Si cap SiGe device by 0.3 V. However, it was found that halo implantation causes the reverse short channel effect (RSCE) on the devices, which can result in Vth roll-up with reducing channel length. The effect of the RSCE becomes greater with increasing Si cap thicknesses of the SiGe devices. Also, non-halo implanted devices were found to demonstrate the RSCE. This is due to excess interstitials from the source/drain implant and their subsequent diffusion, which causes virtual halo dopant to form in non-halo implanted devices.