Si-based MOSFETs Research Articles

A New Type of Si-Based MOSFET for Radiation Reinforcement.

This paper thoroughly analyses the role of drift in the sensitive region in the single-event effect (SEE), with the aim of enhancing the single-particle radiation resistance of N-type metal-oxide semiconductor field-effect transistors (MOSFETs). It proposes a design for a Si-based device structure that extends the lightly doped source-drain region of the N-channel metal-oxide semiconductor (NMOS), thereby moderating the electric field of the sensitive region. This design leads to a 15.69% decrease in the charge collected at the leaky end of the device under the standard irradiation conditions. On this basis, a device structure is further proposed to form a composite metal-oxide semiconductor (MOS) by connecting a pn junction at the lightly doped source-drain end. By adding two charge paths, the leakage collection charge is further reduced by 13.85% under standard irradiation conditions. Moreover, the deterioration of the drive current in the purely growing lightly doped source-drain region can be further improved. Simulations of single-event effects under different irradiation conditions show that the device has good resistance to single-event irradiation, and the composite MOS structure smoothly converges to a 14.65% reduction in drain collection charge between 0.2 pC/μm and 1 pC/μm Linear Energy Transfer (LET) values. The incidence position at the source-to-channel interface collects the highest charge reduction rate of 28.23%. The collecting charge reduction rate is maximum, at 17.12%, when the incidence is at a 45-degree angle towards the source.

(Invited) Review of Identification Methods of 1/f Noise Mechanisms in Polymer-Based OTFTs

We study the low frequency noise, also known as flicker noise (1/f), in polymer-based Organic Thin Film Transistors, and we review techniques to identify the mechanisms of the 1/f noise based on a specific model of the device. We found that the quality of the gate dielectric and its interface may determine the dominant noise mechamism.Three theories have been formulated to explain the origin of 1/f noise in FET devices: the carrier number fluctuation (∆N) theory[1], the mobility fluctuation (∆µ) theory [2], and the ∆N - ∆µ theory [3], which assumes that effects of insulator charge fluctuations affect the carrier mobility at the interface. The ∆N - ∆µ theory reduces to the ∆N model when the surface mobility is not affected by carrier number fluctuation.According to the ∆N - ∆µ theory [3]the plot of SID(f)/ID 2 and [gm/ID]2 against ID (gm being the transconductance and ID the drain current) allows us to identify the noise mechanism. When both curves are parallel, 1/f noise must be due to carrier number fluctuation. If there is a slight deviation from this parallel behavior, it must be due to the correlated surface mobility fludtuation (∆N - ∆µ model).A number of analysis of the noise in OTFTs have been published. In most of them, it is found to be a bulk phenomenon[4,5], and as a result the main mechanism is assumed to be mobility fluctuation. However, very often these analysis are not very complete and are based on crystalline MOSFET models instead of specific OTFT models. On the other hand, it was demonstrated that the analysis must be made over a range wide of bias in order to accurately determine the origin of noise [6,7].We studied the origin of 1/f noise two polymeric p-type OTFT technologies developed by CEA´Liten (France).We found that in the older technology the slopes, in log-log scale, of SID(f)/ID 2 and [gm/ID]2, versus ID had quite different values. This means that the main mechanism of noise in OTFTs is not the fluctuation of the number of carriers. Plotting SID(f)/I2 Dvs (VGS-Vth) in log-log scale (Vth being the threshold voltage) for devices with different channel lengths, channel width W=2000 µm and at VDS = 1 V, we observed that the extracted slope is close to -1 (Table 1). This indicates that noise is due to the fluctuation of carrier mobility, due to the lower quality of the materials and fabrication defects. The threshold voltage was extracted assuming a physically-based OTFT model with a power-law based model of the field effect mobility [8].In the second technology, mobility values are higher, 2-3 cm2/(V s). The normalized current noise PSD follows the squared-transconductance ratio variation (Fig. 1), not the inverse of the drain current. We concluded that the low frequency in the targeted devices of the second technology is originated from the carrier number fluctuation due to trapping/release of charge carriers by trap states uniformly distributed within the gate oxide. The extracted values of gate dielectric trap-states density are comparable to values obtained in conventional Si-based MOSFETs [7], indicating the higher quality of the gate dielectric and its interface with the polymeric material compared to the first studied technology and other previously reported OTFT devices.[1] McWhorter A. L.. "1/f noise and germanium surface prosperities," Semiconductor Surface Physics. R. H. Kingdton (Ed), University of Pennsylvania Press, Philadelphia, PA, 1957, pp. 207-228.[2] Hooge F. N., "1/f noise is no surface effect", Physics Letters, 29A (3), 1969, 139–140[3] Ghibaudo, G., et al..,‘Improved analysis of low frequency noise in field-effect MOS transistors’, Phys. Status Solidi. A , 1991, 124, pp. 571-581[4] L. Ke, S., et al., “Low frequency noise analysis on organic thin film transistors,” Journal of Applied Physics 104, 124502 (2008).[5] H. Kang and V. Subramanian, “Measurement and analysis of 1/f noise under switched bias in organic thin film transistors,” Applied Physics Letters 104, 023301 (2014).[6] Y. Xu, et al., “Origin of low-frequency noise in pentacene field-effect transistors,” Solid-State Electronics 61, 106–110 (2011).[7] W. E. Muhea, et al.. “1/f noise analysis in high mobility polymer-based OTFTs with non-fluorinated dielectric,” Appl. Phys. Lett. 114, 243301 (2019).[8] C.H. Kim; et al., “A Compact Model for Organic Field-Effect Transistors With Improved Output Asymptotic Behaviors,” IEEE Trans. on Electron Devices, vol. 60, no. 3, pp. 1136-1141, March 2013. Figure 1

3D assembly of carbon nanotubes for fabrication of field-effect transistors through nanomanipulation and electron-beam-induced deposition

Three-dimensional carbon nanotube field-effect transistors (3D CNTFETs) possess predictable characteristics that rival those of planar CNTFETs and Si-based MOSFETs. However, due to the lack of a reliable assembly technology, they are rarely reported on, despite the amount of attention they receive. To address this problem, we propose the novel concept of a 3D CNTFET and develop its assembly strategy based on nanomanipulation and the electron-beam-induced deposition (EBID) technique inside a scanning electron microscope (SEM). In particular, the electrodes in our transistor design are three metallic cuboids of the same size, and their front, top and back surfaces are all wrapped up in CNTs. The assembly strategy is employed to build the structure through a repeated basic process of pick-up, placement, fixing and cutting of CNTs. The pick-up and placement is performed through one nanomanipulator with four degrees of freedom. Fixing is carried out through the EBID technique so as to improve the mechanical and electrical characteristics of the CNT/electrodes connection. CNT cutting is undertaken using the typical method of electrical breakdown. Experimental results showed that two CNTs were successfully assembled on the front sides of the cubic electrodes. This validates our assembly method for the 3D CNTFET. Also, when contact resistance was measured, tens of kilohms of resistance was observed at the CNT-EBID deposition-FET electrodes junction.. This manifests the electrical reliability of our assembly strategy.

Impact of Energy Relaxation of Channel Electrons on Drain-Induced Barrier Lowering in Nano-Scale Si-Based MOSFETs

Impact of Energy Relaxation of Channel Electrons on Drain-Induced Barrier Lowering in Nano-Scale Si-Based MOSFETs

Epitaxial lanthanide oxide thin films on Si for high-k gate dielectric application: Growth optimization and defect passivation

Abstract

Comparison between Si/SiO2 and InP/Al2O3 based MOSFETs

Electron transport properties of InP-based MOSFET as a new channel material with Al2O3 as a high-k dielectric oxide layer in comparison with Si-based MOSFET are studied by the ensemble Monte Carlo simulation method in which the conduction band valleys in InP are based on three valley models with consideration of quantum effects (effective potential approach). Id–Vd characteristics for Si-based MOSFET are in good agreement with theoretical and experimental results. Our results show that Id of InP-based MOSFET is about 2 times that of Si-based MOSFET. We simulated the diagrams of longitudinal and transverse electric fields, conduction band edge, average electron velocity, and average electron energy for Si-based MOSFET and compared the results with those for InP-based MOSFET. Our results, as was expected, show that the transverse electric field, the conduction band edge, the electron velocity, and the electron energy in a channel in the InP-based MOSFET are greater than those for Si-based MOSFET. But the longitudinal electric field behaves differently at different points of the channel.

Single-Ion Implantation for the Development of Si-Based MOSFET Devices with Quantum Functionalities

Interest in single-ion implantation is driven in part by research into development of solid-state devices that exhibit quantum behaviour in their electronic or optical characteristics. Here, we provide an overview of international research work on single ion implantation and single ion detection for development of electronic devices for quantum computing. The scope of international research into single ion implantation is presented in the context of our own research in the Centre for Quantum Computation and Communication Technology in Australia. Various single ion detection schemes are presented, and limitations on dopant placement accuracy due to ion straggling are discussed together with pathways for scale-up to multiple quantum devices on the one chip. Possible future directions for ion implantation in quantum computing and communications are also discussed.

Two-dimensional quantum mechanical simulation of electron transport in nano-scaled Si-based MOSFETs

As the transistor dimensions scale down below the 100 nm regime, the reliability of semiclassical models of transport decreases. To offer additional insight into transport phenomena in these deeply scaled devices, simulation tools that treat non-local quantum transport and confinement effects without sacrificing the realistic treatment of scattering are needed. A unique non-equilibrium Green's function approach “Schrödinger equation Monte-Carlo” (SEMC) provides a physically rigorous approach to quantum transport and phase-breaking inelastic scattering via real ( actual) scattering processes such as optical and acoustic phonon scattering. “One-dimensional” SEMC codes previously have been applied to model transport in systems such as quantum well lasers where the potential varies only along the nominal direction of transport, although with a fully three-dimensional (3D) treatment of scattering. In this paper, the development of a version of “SEMC-2D” code for electrostatically self-consistent treatment of quantum transport within devices with, additionally, quantum confinement normal to the direction of transport, is reported along with illustrative simulation results for nano-scaled SOI MOSFETs geometries.

Simulation of quantum effects along the channel of ultrascaled Si-based MOSFETs

Quantum transport simulations, including phase-breaking scattering, are used to observe the transition from classical to quantum transport in ultrascaled Si and SiGe heterostructure MOSFETs in order to gauge the potential effectiveness of semiclassical and pure phase-coherent quantum transport models as this transition is approached. It is shown that semiclassical models of transport along the length of the channel (as opposed to normal to the channel, where the importance of quantum mechanical effects has long been recognized) may remain reliable for channel lengths down to roughly 10 nm and perhaps beyond, and likely more reliable at this point than phase-coherent quantum transport simulations even when much of the transport is coherent/ballistic. As coherent transport effects within the channel eventually do become significant for ballistic carriers, the phase-breaking scattering rate, itself, also becomes a nonlocal function of the carrier's kinetic energy placing further demands on simulation. Simulations also reaffirm that for injection into the channel, the modeling of quantum transport effects such as tunneling, particularly in Si-SiGe heterostructure MOSFET's, will be important in much longer devices. However, even for this purpose it may not be possible to neglect the effects of inelastic scattering that can provide additional tunneling "paths.".